Entity sync_Vector

Block Diagram of sync_Vector

This module synchronizes a vector of bits from clock-domain Clock1 to clock-domain Clock2. The clock-domain boundary crossing is done by a change comparator, a T-FF, two synchronizer D-FFs and a reconstructive XOR indicating a value change on the input. This changed signal is used to capture the input for the new output. A busy flag is additionally calculated for the input clock domain.

Constraints:

This module uses sub modules which need to be constrained. Please attend to the notes of the instantiated sub modules.

Generics

Name	Type	Default	Description
MASTER_BITS	positive	8	number of bit to be synchronized
SLAVE_BITS	natural	0
INIT	std_logic_vector	x"00000000"
SYNC_DEPTH	T_MISC_SYNC_DEPTH	low	generate SYNC_DEPTH many stages, at least 2

Ports

Name	Type	Direction	Description
Clock1	std_logic	in	<Clock> input clock
Clock2	std_logic	in	<Clock> output clock
Input	std_logic_vector	in	@Clock1: input vector
Output	std_logic_vector	out	@Clock2: output vector
Busy	std_logic	out	@Clock1: busy bit
Changed	std_logic	out	@Clock2: changed bit

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