[source]

Component arith_prng

BITSSEEDclkstd_logicrststd_logicgotstd_logicvalstd_logic_vector[BITS - 1 downto 0]

Block Diagram of arith_prng

Generics

Name

Type

Initial Value

Description

BITS

positive

SEED

std_logic_vector

"0"

Ports

Name

Direction

Type

Description

clk

in

std_logic

rst

in

std_logic

got

in

std_logic

val

out

std_logic_vector