[source]

Entity stream_Buffer

FRAMESDATA_BITSDATA_FIFO_DEPTHMETA_BITSMETA_FIFO_DEPTHClockstd_logicResetstd_logicIn_Validstd_logicIn_Data[DATA_BITS - 1 downto 0]std_logic_vectorIn_SOFstd_logicIn_EOFstd_logicIn_Meta_Data[isum ( META_BITS ) - 1 downto 0]std_logic_vectorOut_Ackstd_logicOut_Meta_rststd_logicOut_Meta_nxt[META_BITS ' length - 1 downto 0]std_logic_vectorIn_Ackstd_logicIn_Meta_rststd_logicIn_Meta_nxtstd_logic_vector[META_BITS ' length - 1 downto 0]Out_Validstd_logicOut_Datastd_logic_vector[DATA_BITS - 1 downto 0]Out_SOFstd_logicOut_EOFstd_logicOut_Meta_Datastd_logic_vector[isum ( META_BITS ) - 1 downto 0]

Block Diagram of stream_Buffer

This module implements a generic buffer (FIFO) for the PoC.Stream </Interfaces/Stream> protocol. It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for data and meta information.

Generics

Name

Type

Default

Description

FRAMES

positive

2

DATA_BITS

positive

8

DATA_FIFO_DEPTH

positive

8

META_BITS

T_POSVEC

(0 => 8)

META_FIFO_DEPTH

T_POSVEC

(0 => 16)

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

In_Valid

std_logic

in

IN Port

In_Data

std_logic_vector

in

In_SOF

std_logic

in

In_EOF

std_logic

in

In_Ack

std_logic

out

In_Meta_rst

std_logic

out

In_Meta_nxt

std_logic_vector

out

In_Meta_Data

std_logic_vector

in

Out_Valid

std_logic

out

OUT Port

Out_Data

std_logic_vector

out

Out_SOF

std_logic

out

Out_EOF

std_logic

out

Out_Ack

std_logic

in

Out_Meta_rst

std_logic

in

Out_Meta_nxt

std_logic_vector

in

Out_Meta_Data

std_logic_vector

out