Architecture rtl of sdram_ctrl_fsm
Name  | 
Description  | 
|---|---|
FSM_TYPE  | 
  | 
SD_CMD_TYPE  | 
  | 
SD_A_SEL_TYPE  | 
|
SD_BA_SEL_TYPE  | 
Functions
- burst_clock_cycles()
 length of burst in clock cycles of "clk"
Processes
- process @(clk)
 Registers
#  | 
Current State  | 
Next State  | 
Condition  | 
Comment  | 
|---|---|---|---|---|
1  | 
INIT1  | 
INIT2  | 
[EMPTY]  | 
|
2  | 
INIT2  | 
INIT3  | 
[((timer_tREFI_done = '1') and (downcnt_done = '1'))]  | 
|
3  | 
INIT3  | 
INIT4  | 
[EMPTY]  | 
|
4  | 
INIT4  | 
INIT5  | 
[(SDRAM_TYPE >= 1)]  | 
|
5  | 
INIT4  | 
INIT8  | 
[not (SDRAM_TYPE >= 1)]  | 
|
6  | 
INIT5  | 
INIT6  | 
[(timer_cmd_done = '1')]  | 
|
7  | 
INIT8  | 
INIT9  | 
[(timer_cmd_done = '1')]  | 
|
8  | 
INIT6  | 
INIT7  | 
[(timer_cmd_done = '1')]  | 
|
9  | 
INIT9  | 
INIT10  | 
[(timer_cmd_done = '1')]  | 
|
10  | 
INIT7  | 
INIT8  | 
[(timer_cmd_done = '1')]  | 
|
11  | 
INIT10  | 
INIT11  | 
[(timer_cmd_done = '1' and timer_tREFI_done = '1')]  | 
|
12  | 
INIT11  | 
DO_ACTIVATE  | 
[(timer_cmd_done = '1')]  | 
|
13  | 
DO_ACTIVATE  | 
DO_WRITE1  | 
[((timer_cmd_done = '1') and (user_cmd_valid = '1') and (user_write = '1'))]  | 
|
14  | 
DO_ACTIVATE  | 
DO_READ1  | 
[((timer_cmd_done = '1') and (user_cmd_valid = '1') and not (user_write = '1'))]  | 
|
15  | 
DO_WRITE1  | 
CHECKNXT  | 
[((timer_cmd_done and user_wdata_valid = '1') and (SDRAM_TYPE = 0 and BL = 1 or SDRAM_TYPE > 0 and BL = 2))]  | 
|
16  | 
DO_WRITE1  | 
DO_WRITE2  | 
[((timer_cmd_done and user_wdata_valid = '1') and not (SDRAM_TYPE = 0 and BL = 1 or SDRAM_TYPE > 0 and BL = 2))]  | 
|
17  | 
DO_READ1  | 
CHECKNXT  | 
[((timer_cmd_done = '1') and (SDRAM_TYPE = 0 and BL = 1 or SDRAM_TYPE > 0 and BL = 2))]  | 
|
18  | 
DO_READ1  | 
DO_READ2  | 
[((timer_cmd_done = '1') and not (SDRAM_TYPE = 0 and BL = 1 or SDRAM_TYPE > 0 and BL = 2))]  | 
|
19  | 
CHECKNXT  | 
DO_PRECHARGE  | 
[((timer_tREFI_done = '1') and (timer_tRAS_done = '1')), (not (timer_tREFI_done = '1') and not (user_cmd_valid and same_bank_row = '1') and (timer_cmd_done = '1') and (timer_tRAS_done = '1'))]  | 
|
20  | 
CHECKNXT  | 
DO_WRITE1  | 
[(not (timer_tREFI_done = '1') and (user_cmd_valid and same_bank_row = '1') and (user_write = '1'))]  | 
|
21  | 
CHECKNXT  | 
DO_READ1  | 
[(not (timer_tREFI_done = '1') and (user_cmd_valid and same_bank_row = '1') and not (user_write = '1'))]  | 
|
22  | 
DO_WRITE2  | 
CHECKNXT  | 
[((SDRAM_TYPE = 0 and BL > 1 or SDRAM_TYPE > 0 and BL > 2) and (downcnt_done = '1'))]  | 
|
23  | 
DO_READ2  | 
CHECKNXT  | 
[((SDRAM_TYPE = 0 and BL > 1 or SDRAM_TYPE > 0 and BL > 2) and (downcnt_done = '1'))]  | 
|
24  | 
DO_PRECHARGE  | 
DO_AUTO_REFRESH  | 
[((timer_cmd_done = '1') and (timer_tREFI_done = '1'))]  | 
|
25  | 
DO_PRECHARGE  | 
DO_ACTIVATE  | 
[((timer_cmd_done = '1') and not (timer_tREFI_done = '1'))]  | 
|
26  | 
DO_AUTO_REFRESH  | 
DO_ACTIVATE  | 
[(timer_cmd_done = '1')]  |