Entity misc_Delay

Block Diagram of misc_Delay

Generics

Name	Type	Default	Description
BITS	positive
TAPS	T_NATVEC		select one or multiple delay tap points

Ports

Name	Type	Direction	Description
Clock	std_logic	in	clock
Reset	std_logic	in	reset; avoid reset to enable SRL16/SRL32 usage
Enable	std_logic	in	enable
DataIn	std_logic_vector	in	data to delay
DataOut	T_SLM	out	delayed ouputs, tapped at TAPS(i)

• Architecture rtl of misc_Delay

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