Entity arith_addw

Block Diagram of arith_addw

Implements wide addition providing several options all based on an adaptation of a carry-select approach.

References:

Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:

FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, FPL 2011. -> ARCH: AAM, CAI, CCA -> SKIPPING: CCC

Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:

A Novel Modular Adder for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs, FPL 2014. -> ARCH: PAI -> SKIPPING: PPN_KS, PPN_BK

Generics

Name	Type	Default	Description
N	positive		Operand Width
K	positive		Block Count
ARCH	tArch	AAM	Architecture
BLOCKING	tBlocking	DFLT	Blocking Scheme
SKIPPING	tSkipping	CCC	Carry Skip Scheme
P_INCLUSIVE	boolean	false	Use Inclusive Propagate, i.e. c^1

Ports

Name	Type	Direction	Description
a	std_logic_vector	in
b	std_logic_vector	in
cin	std_logic	in
s	std_logic_vector	out
cout	std_logic	out

• Architecture rtl of arith_addw
  • Functions

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