[source]

Entity stat_Histogram

DATA_BITSCOUNTER_BITSClockstd_logicResetstd_logicEnablestd_logicDataIn[DATA_BITS - 1 downto 0]std_logic_vectorHistogramT_SLM[2 ** DATA_BITS - 1 downto 0 , COUNTER_BITS - 1 downto 0]

Block Diagram of stat_Histogram

Generics

Name

Type

Default

Description

DATA_BITS

positive

16

COUNTER_BITS

positive

16

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Enable

std_logic

in

DataIn

std_logic_vector

in

Histogram

T_SLM

out