Architecture rtl of cache_cpu

Types

Name	Description
T_FSM	FSM and other state registers

Processes

process

process @(clk)

FSM Transitions for fsm_cs

#	Current State	Next State	Condition	Comment
1	READING_MEM	READY	[(to_x01(mem_rstb) when '1')]
2	READING_MEM	UNKNOWN	[(to_x01(mem_rstb) when others)]
3	READY	ACCESS_MEM	[(cache_Hit and cpu_write or cache_Miss when '1')]
4	READY	UNKNOWN	[(cache_Hit and cpu_write or cache_Miss when others)]
5	ACCESS_MEM	READY	[((to_x01(mem_rdy) when '1') and (to_x01(cpu_write) when '1'))]	write
6	ACCESS_MEM	READING_MEM	[((to_x01(mem_rdy) when '1') and (to_x01(cpu_write) when '0'))]	read
7	ACCESS_MEM	UNKNOWN	[(to_x01(mem_rdy) when others), ((to_x01(mem_rdy) when '1') and (to_x01(cpu_write) when others))]	invalid input invalid input

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