[source]

Component arith_div

A_BITSD_BITSRAPOWPIPELINEDclkstd_logicrststd_logicstartstd_logicA[A_BITS - 1 downto 0]std_logic_vectorD[D_BITS - 1 downto 0]std_logic_vectorreadystd_logicQstd_logic_vector[A_BITS - 1 downto 0]Rstd_logic_vector[D_BITS - 1 downto 0]Zstd_logic

Block Diagram of arith_div

Generics

Name

Type

Initial Value

Description

A_BITS

positive

Dividend Width

D_BITS

positive

Divisor Width

RAPOW

positive

1

Power of Compute Radix (2**RAPOW)

PIPELINED

boolean

false

Computation Pipeline

Ports

Name

Direction

Type

Description

clk

in

std_logic

Global Reset/Clock

rst

in

std_logic

start

in

std_logic

Ready / Start

ready

out

std_logic

A

in

std_logic_vector

Arguments / Result (2's complement) Dividend

D

in

std_logic_vector

Divisor

Q

out

std_logic_vector

Quotient

R

out

std_logic_vector

Remainder

Z

out

std_logic

Division by Zero