[source]

Component arith_carrychain_inc_xilinx

BITSX[BITS - 1 downto 0]std_logic_vectorCInstd_logicYstd_logic_vector[BITS - 1 downto 0]

Block Diagram of arith_carrychain_inc_xilinx

Generics

Name

Type

Initial Value

Description

BITS

positive

Ports

Name

Direction

Type

Description

X

in

std_logic_vector

CIn

in

std_logic

Y

out

std_logic_vector