[source]

Entity comm_scramble

GENBITSclkstd_logicsetstd_logicdin[GEN ' length - 2 downto 0]std_logic_vectorstepstd_logicmaskstd_logic_vector[BITS - 1 downto 0]

Block Diagram of comm_scramble

The LFSR computation is unrolled to generate an arbitrary number of mask bits in parallel. The mask are output in little endian. The generated bit sequence is independent from the chosen output width.

Generics

Name

Type

Default

Description

GEN

bit_vector

Generator Polynomial (little endian)

BITS

positive

Width of Mask Bits to be computed in parallel in each step

Ports

Name

Type

Direction

Description

clk

std_logic

in

Clock

set

std_logic

in

Set LFSR to value provided on din

din

std_logic_vector

in

step

std_logic

in

Compute a Mask Output

mask

std_logic_vector

out