Entity stream_Mux

Block Diagram of stream_Mux

Generics

Name	Type	Default	Description
PORTS	positive	2
DATA_BITS	positive	8
META_BITS	natural	8
META_REV_BITS	natural	2	;

Ports

Name	Type	Direction	Description
Clock	std_logic	in
Reset	std_logic	in
In_Valid	std_logic_vector	in	IN Ports
In_Data	T_SLM	in
In_Meta	T_SLM	in
In_Meta_rev	T_SLM	out
In_SOF	std_logic_vector	in
In_EOF	std_logic_vector	in
In_Ack	std_logic_vector	out
Out_Valid	std_logic	out	OUT Port
Out_Data	std_logic_vector	out
Out_Meta	std_logic_vector	out
Out_Meta_rev	std_logic_vector	in
Out_SOF	std_logic	out
Out_EOF	std_logic	out
Out_Ack	std_logic	in

• Architecture rtl of stream_Mux
  • Processes

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