[source]

Entity arith_div

A_BITSD_BITSRAPOWPIPELINEDclkstd_logicrststd_logicstartstd_logicA[A_BITS - 1 downto 0]std_logic_vectorD[D_BITS - 1 downto 0]std_logic_vectorreadystd_logicQstd_logic_vector[A_BITS - 1 downto 0]Rstd_logic_vector[D_BITS - 1 downto 0]Zstd_logic

Block Diagram of arith_div

Implementation of a Non-Performing restoring divider with a configurable radix. The multi-cycle division is controlled by 'start' / 'rdy'. A new division is started by asserting 'start'. The result Q = A/D is available when 'rdy' returns to '1'. A division by zero is identified by output Z. The Q and R outputs are undefined in this case.

Generics

Name

Type

Default

Description

A_BITS

positive

Dividend Width

D_BITS

positive

Divisor Width

RAPOW

positive

1

Power of Compute Radix (2**RAPOW)

PIPELINED

boolean

false

Computation Pipeline

Ports

Name

Type

Direction

Description

clk

std_logic

in

Global Reset/Clock

rst

std_logic

in

start

std_logic

in

Ready / Start

ready

std_logic

out

A

std_logic_vector

in

Arguments / Result (2's complement) Dividend

D

std_logic_vector

in

Divisor

Q

std_logic_vector

out

Quotient

R

std_logic_vector

out

Remainder

Z

std_logic

out

Division by Zero