Entity sync_Strobe

Block Diagram of sync_Strobe

This module synchronizes multiple high-active bits from clock-domain Clock1 to clock-domain Clock2. The clock-domain boundary crossing is done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy flag is additionally calculated and can be used to block new inputs. All bits are independent from each other. Multiple consecutive strobes are suppressed by a rising edge detection.

Attention

Use this synchronizer only for one-cycle high-active signals (strobes).

Constraints:

This module uses sub modules which need to be constrained. Please attend to the notes of the instantiated sub modules.

Generics

Name	Type	Default	Description
BITS	positive	1	number of bit to be synchronized
GATED_INPUT_BY_BUSY	boolean	TRUE	use gated input (by busy signal)
SYNC_DEPTH	T_MISC_SYNC_DEPTH	low	generate SYNC_DEPTH many stages, at least 2

Ports

Name	Type	Direction	Description
Clock1	std_logic	in	<Clock> input clock domain
Clock2	std_logic	in	<Clock> output clock domain
Input	std_logic_vector	in	@Clock1: input bits
Output	std_logic_vector	out	@Clock2: output bits
Busy	std_logic_vector	out	@Clock1: busy bits

×