Architecture rtl of sortnet_MergeSort_Streamed

Types

Name	Description
T_FIFO_DATA
T_STATE

Processes

process

process @(Out_Ack or Switch or FIFO_1_DataOut or FIFO_1_Valid or FIFO_0_DataOut or FIFO_0_Valid or State)

FSM Transitions for State

#	Current State	Next State	Condition	Comment
1	ST_IDLE	ST_MERGE	[((FIFO_0_Valid and FIFO_1_Valid = '1') and (FIFO_0_SOF and FIFO_1_SOF = '1'))]
2	ST_MERGE	ST_EMPTY_FIFO_1	[((FIFO_0_Valid and FIFO_1_Valid = '1') and (FIFO_0_EOF = '1'))]
3	ST_MERGE	ST_EMPTY_FIFO_0	[((FIFO_0_Valid and FIFO_1_Valid = '1') and not (FIFO_0_EOF = '1') and (FIFO_1_EOF = '1'))]
4	ST_EMPTY_FIFO_1	ST_IDLE	[((FIFO_1_Valid = '1') and (FIFO_1_EOF = '1'))]
5	ST_EMPTY_FIFO_0	ST_IDLE	[((FIFO_0_Valid = '1') and (FIFO_0_EOF = '1'))]

×