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Package components

This packages describes common primitives like flip flops and multiplexers as a function to use them as one-liners.

ATTENSION:

The parameter 'constant INIT' of some functions is actually the reset value, not the initial value after device programming (e.g. for FPGAs), this value MUST be set via signal declaration!

Functions

registered(std_logic Clock, boolean IsRegistered)

implement an optional register stage

Parameters:

  • Clock (std_logic)

  • IsRegistered (boolean)

ffrs(std_logic q, std_logic rst = \'0\', std_logic set = \'0\')

FlipFlop functions

RS-FlipFlops

param std_logic q:

param std_logic rst:

param std_logic set:

RS-FlipFlop with dominant rst

ffsr(std_logic q, std_logic rst = \'0\', std_logic set = \'0\')
Parameters:

  • q (std_logic)

  • rst (std_logic)

  • set (std_logic) -- RS-FlipFlop with dominant set

ffdre(std_logic q, std_logic d, std_logic rst = \'0\', std_logic en = \'1\', std_logic INIT = \'0\')

D-FlipFlops (Delay)

Parameters:

  • q (std_logic)

  • d (std_logic)

  • rst (std_logic)

  • en (std_logic)

  • INIT (std_logic) -- D-FlipFlop with reset and enable

ffdre(std_logic_vector q, std_logic_vector d, std_logic rst = \'0\', std_logic en = \'1\', std_logic_vector INIT = ( 0 to 0 => \'0\' ))
Parameters:

  • q (std_logic_vector)

  • d (std_logic_vector)

  • rst (std_logic)

  • en (std_logic)

  • INIT (std_logic_vector) -- D-FlipFlop with reset and enable

ffdse(std_logic q, std_logic d, std_logic set = \'0\', std_logic en = \'1\')
Parameters:

  • q (std_logic)

  • d (std_logic)

  • set (std_logic)

  • en (std_logic) -- D-FlipFlop with set and enable

fftre(std_logic q, std_logic t, std_logic rst = \'0\', std_logic en = \'1\', std_logic INIT = \'0\')

T-FlipFlops (Toggle)

Parameters:

  • q (std_logic)

  • t (std_logic)

  • rst (std_logic)

  • en (std_logic)

  • INIT (std_logic) -- T-FlipFlop with reset and enable

fftse(std_logic q, std_logic t, std_logic set = \'0\', std_logic en = \'1\')
Parameters:

  • q (std_logic)

  • t (std_logic)

  • set (std_logic)

  • en (std_logic) -- T-FlipFlop with set and enable

upcounter_next(unsigned cnt, std_logic rst = \'0\', std_logic en = \'1\', natural INIT = 0)

counter

Parameters:

  • cnt (unsigned)

  • rst (std_logic)

  • en (std_logic)

  • INIT (natural)

upcounter_equal(unsigned cnt, natural value)
Parameters:

  • cnt (unsigned)

  • value (natural)

downcounter_next(signed cnt, std_logic rst = \'0\', std_logic en = \'1\', integer INIT = 0)
Parameters:

  • cnt (signed)

  • rst (std_logic)

  • en (std_logic)

  • INIT (integer)

downcounter_equal(signed cnt, integer value)
Parameters:

  • cnt (signed)

  • value (integer)

downcounter_neg(signed cnt)
Parameters:

cnt (signed)

shreg_left(std_logic_vector q, std_logic i, std_logic en = \'1\')

shiftregisters

Parameters:

  • q (std_logic_vector)

  • i (std_logic)

  • en (std_logic)

shreg_right(std_logic_vector q, std_logic i, std_logic en = \'1\')
Parameters:

  • q (std_logic_vector)

  • i (std_logic)

  • en (std_logic)

rreg_left(std_logic_vector q, std_logic en = \'1\')

rotate registers

Parameters:

  • q (std_logic_vector)

  • en (std_logic)

rreg_right(std_logic_vector q, std_logic en = \'1\')
Parameters:

  • q (std_logic_vector)

  • en (std_logic)

comp(std_logic_vector value1, std_logic_vector value2)

compare

Parameters:

  • value1 (std_logic_vector)

  • value2 (std_logic_vector)

comp(unsigned value1, unsigned value2)
Parameters:

  • value1 (unsigned)

  • value2 (unsigned)

comp(signed value1, signed value2)
Parameters:

  • value1 (signed)

  • value2 (signed)

comp_allzero(std_logic_vector value)
Parameters:

value (std_logic_vector)

comp_allzero(unsigned value)
Parameters:

value (unsigned)

comp_allzero(signed value)
Parameters:

value (signed)

comp_allone(std_logic_vector value)
Parameters:

value (std_logic_vector)

comp_allone(unsigned value)
Parameters:

value (unsigned)

comp_allone(signed value)
Parameters:

value (signed)

mux(std_logic sel, std_logic sl0, std_logic sl1)

multiplexing

Parameters:

  • sel (std_logic)

  • sl0 (std_logic)

  • sl1 (std_logic)

mux(std_logic sel, std_logic_vector slv0, std_logic_vector slv1)
Parameters:

  • sel (std_logic)

  • slv0 (std_logic_vector)

  • slv1 (std_logic_vector)

mux(std_logic sel, unsigned us0, unsigned us1)
Parameters:

  • sel (std_logic)

  • us0 (unsigned)

  • us1 (unsigned)

mux(std_logic sel, signed s0, signed s1)
Parameters:

  • sel (std_logic)

  • s0 (signed)

  • s1 (signed)