[source]

Entity sortnet_MergeSort_Streamed

FIFO_DEPTHKEY_BITSDATA_BITSClockstd_logicResetstd_logicInversestd_logicIn_Validstd_logicIn_Data[DATA_BITS - 1 downto 0]std_logic_vectorIn_SOFstd_logicIn_IsKeystd_logicIn_EOFstd_logicOut_Ackstd_logicIn_Ackstd_logicOut_Syncstd_logicOut_Validstd_logicOut_Datastd_logic_vector[DATA_BITS - 1 downto 0]Out_SOFstd_logicOut_IsKeystd_logicOut_EOFstd_logic

Block Diagram of sortnet_MergeSort_Streamed

Generics

Name

Type

Default

Description

FIFO_DEPTH

positive

32

KEY_BITS

positive

32

DATA_BITS

positive

32

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Inverse

std_logic

in

In_Valid

std_logic

in

In_Data

std_logic_vector

in

In_SOF

std_logic

in

In_IsKey

std_logic

in

In_EOF

std_logic

in

In_Ack

std_logic

out

Out_Sync

std_logic

out

Out_Valid

std_logic

out

Out_Data

std_logic_vector

out

Out_SOF

std_logic

out

Out_IsKey

std_logic

out

Out_EOF

std_logic

out

Out_Ack

std_logic

in