Entity gearbox_up_cc

Block Diagram of gearbox_up_cc

This module provides a downscaling gearbox with a common clock (cc) interface. It perfoems a 'byte' to 'word' collection. The default order is LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" are of the same clock domain "Clock". Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Generics

Name	Type	Default	Description
INPUT_BITS	positive	24
OUTPUT_BITS	positive	32
META_BITS	natural	0
ADD_INPUT_REGISTERS	boolean	FALSE
ADD_OUTPUT_REGISTERS	boolean	FALSE

Ports

Name	Type	Direction	Description
Clock	std_logic	in
In_Sync	std_logic	in
In_Valid	std_logic	in
In_Data	std_logic_vector	in
In_Meta	std_logic_vector	in
Out_Sync	std_logic	out
Out_Valid	std_logic	out
Out_Data	std_logic_vector	out
Out_Meta	std_logic_vector	out
Out_First	std_logic	out
Out_Last	std_logic	out

• Architecture rtl of gearbox_up_cc
  • Functions

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