[source]

Entity stat_Minimum

DEPTHDATA_BITSCOUNTER_BITSClockstd_logicResetstd_logicEnablestd_logicDataIn[DATA_BITS - 1 downto 0]std_logic_vectorValidsstd_logic_vector[DEPTH - 1 downto 0]MinimumsT_SLM[DEPTH - 1 downto 0 , DATA_BITS - 1 downto 0]CountsT_SLM[DEPTH - 1 downto 0 , COUNTER_BITS - 1 downto 0]

Block Diagram of stat_Minimum

Generics

Name

Type

Default

Description

DEPTH

positive

8

DATA_BITS

positive

16

COUNTER_BITS

positive

16

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Enable

std_logic

in

DataIn

std_logic_vector

in

Valids

std_logic_vector

out

Minimums

T_SLM

out

Counts

T_SLM

out