Entity arith_same

Block Diagram of arith_same

This circuit may, for instance, be used to detect the first sign change and, thus, the range of a two's complement number.

These components may be chained by using the output of the predecessor as guard input. This chaining allows to have intermediate results available while still ensuring the use of a fast carry chain on supporting FPGA architectures. When chaining, make sure to overlap both vector slices by one bit position as to avoid an undetected sign change between the slices.

Generics

Name	Type	Default	Description
N	positive		Input width

Ports

Name	Type	Direction	Description
g	std_logic	in	Guard Input (!g => !y)
x	std_logic_vector	in	Input Vector
y	std_logic	out	All-same Output

×