[source]

Entity bus_Arbiter

STRATEGYPORTSWEIGHTSOUTPUT_REGClockstd_logicResetstd_logicArbitratestd_logicRequest_Vector[PORTS - 1 downto 0]std_logic_vectorArbitratedstd_logicGrant_Vectorstd_logic_vector[PORTS - 1 downto 0]Grant_Indexstd_logic_vector[log2ceilnz ( PORTS ) - 1 downto 0]

Block Diagram of bus_Arbiter

This module implements a generic arbiter. It currently supports the following arbitration strategies:

Round Robin (RR)

Generics

Name

Type

Default

Description

STRATEGY

string

"RR"

RR, LOT

PORTS

positive

1

WEIGHTS

T_INTVEC

(0 => 1)

OUTPUT_REG

boolean

TRUE

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Arbitrate

std_logic

in

Request_Vector

std_logic_vector

in

Arbitrated

std_logic

out

Grant_Vector

std_logic_vector

out

Grant_Index

std_logic_vector

out