Component fifo_glue

Block Diagram of fifo_glue

Minimal FIFO with single clock to decouple enable domains.

Generics

Name	Type	Initial Value	Description
D_BITS	positive		Data Width

Ports

Name	Direction	Type	Description
clk	in	std_logic	Control Clock
rst	in	std_logic	Synchronous Reset
put	in	std_logic	Input Put Value
di	in	std_logic_vector	Data Input
ful	out	std_logic	Full
vld	out	std_logic	Output Data Available
do	out	std_logic_vector	Data Output
got	in	std_logic	Data Consumed

×