Component fifo_ic_assembly

Block Diagram of fifo_ic_assembly

Generics

Name	Type	Initial Value	Description
D_BITS	positive		Data Width
A_BITS	positive		Address Bits
G_BITS	positive		Generation Guard Bits

Ports

Name	Direction	Type	Description
clk_wr	in	std_logic	Write Interface
rst_wr	in	std_logic
base	out	std_logic_vector	Only write addresses in the range [base, base+2**(A_BITS-G_BITS)) are acceptable. This is equivalent to the test tmp(A_BITS-1 downto A_BITS-G_BITS) = 0 where tmp = addr - base. Writes performed outside the allowable range will assert the failure indicator, which will stick until the next reset. No write is to be performed before base turns zero (0) for the first time.
failed	out	std_logic
addr	in	std_logic_vector
din	in	std_logic_vector
put	in	std_logic
clk_rd	in	std_logic	Read Interface
rst_rd	in	std_logic
dout	out	std_logic_vector
vld	out	std_logic
got	in	std_logic

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