Component fifo_ic_got

Block Diagram of fifo_ic_got

Generics

Name	Type	Initial Value	Description
D_BITS	positive		Data Width
MIN_DEPTH	positive		Minimum FIFO Depth
DATA_REG	boolean	false	Store Data Content in Registers
OUTPUT_REG	boolean	false	Registered FIFO Output
ESTATE_WR_BITS	natural	0	Empty State Bits
FSTATE_RD_BITS	natural	0	Full State Bits

Ports

Name	Direction	Type	Description
clk_wr	in	std_logic	Write Interface
rst_wr	in	std_logic
put	in	std_logic
din	in	std_logic_vector
full	out	std_logic
estate_wr	out	std_logic_vector
clk_rd	in	std_logic	Read Interface
rst_rd	in	std_logic
got	in	std_logic
valid	out	std_logic
dout	out	std_logic_vector
fstate_rd	out	std_logic_vector

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