[source]

Component fifo_ll_glue

D_BITSFRAME_USER_BITSREGISTER_PATHclkstd_logicresetstd_logicsof_instd_logicdata_in[D_BITS downto 1]std_logic_vectorframe_data_in[imax ( 1 , FRAME_USER_BITS ) downto 1]std_logic_vectoreof_instd_logicsrc_rdy_instd_logicdst_rdy_outstd_logicdst_rdy_instd_logicsof_outstd_logicdata_outstd_logic_vector[D_BITS downto 1]frame_data_outstd_logic_vector[imax ( 1 , FRAME_USER_BITS ) downto 1]eof_outstd_logicsrc_rdy_outstd_logic

Block Diagram of fifo_ll_glue

Minimal Local-Link-FIFO with single clock and first-word-fall-through mode.

Generics

Name

Type

Initial Value

Description

D_BITS

positive

FRAME_USER_BITS

natural

REGISTER_PATH

boolean

Ports

Name

Direction

Type

Description

clk

in

std_logic

reset

in

std_logic

sof_in

in

std_logic

in port

data_in

in

std_logic_vector

frame_data_in

in

std_logic_vector

eof_in

in

std_logic

src_rdy_in

in

std_logic

dst_rdy_in

out

std_logic

sof_out

out

std_logic

out port

data_out

out

std_logic_vector

frame_data_out

out

std_logic_vector

eof_out

out

std_logic

src_rdy_out

out

std_logic

dst_rdy_out

in

std_logic