Commands

This page lists all the commands exposed by the DVT extension.

DVT

Command Name	Command ID	Natures	Description
Activate	dvt.activate.force	All	Enables DVT support for the current workspace.
Build Project (Parser Profile)	dvt.build.buildParserProfile	All	Builds the project and collects thread dumps during parsing.
Cancel Build	dvt.build.cancelBuild	All	Cancels the current build.
Open Build Log	dvt.build.openBuildLogFile	All	Opens the build log file in the editor.
Open Build Output	dvt.build.openBuildOutput	All	Opens the build output panel.
Open Build Report	dvt.build.openBuildReportFile	All	Opens the build report file in the editor.
Rebuild e Language Tests	dvt.build.rebuildETests	e Language	Rebuilds the e Language test files.
Build	dvt.build.startBuild	All	Starts a full build of the project using the current configuration. See Build Configurations.
Show build configuration quick reference	dvt.buildConfig.showQuickReference	All	Shows a short documentation for the selected build configuration.
Show UVM Sequence Tree	dvt.callHierarchy.showUVMSequenceTree	SystemVerilog, e Language	Shows the UVM Sequence Tree for the selected sequence.
Change Languages…	dvt.changeNature	All	Changes the enabled languages (natures) for the current project. See Project Natures.
Clear Code Factory Input	dvt.codeFactory.clearFactoryInput	SystemVerilog, VHDL	Clears the current Code Factory input.
Set Code Factory Input	dvt.codeFactory.setFactoryInput	SystemVerilog, VHDL	Sets the input for the Code Factory.
Collapse Compile Order	dvt.collapseAllCompileOrder	All	Collapses all items in the Compile Order View. See Compile Order View.
Collapse Config DB	dvt.collapseAllConfigDB	SystemVerilog	Collapses all items in the Config DB View.
Collapse Design Hierarchy	dvt.collapseAllDesignHierarchy	SystemVerilog, VHDL	Collapses all items in the Design Hierarchy View.
Collapse Factory Overrides	dvt.collapseAllFactoryOverrides	SystemVerilog	Collapses all items in the Factory Overrides View.
Collapse All Inline Macro Expansions	dvt.collapseAllInlineExpansions	SystemVerilog	Collapses all inline macro expansions.
Collapse Registers	dvt.collapseAllRegisters	SystemVerilog	Collapses all items in the Registers View.
Collapse Verification Hierarchy	dvt.collapseAllVerificationHierarchy	SystemVerilog, e Language	Collapses all items in the Verification Hierarchy View.
Collapse Inline Macro Expansion	dvt.collapseInlineExpansion	SystemVerilog, e Language	Collapses the inline macro expansion of the selected macro.
Collect Project Statistics	dvt.collectProjectStatistics	All	Collects statistics about the current project.
Compare with PVerilog Preprocessed/Generated File	dvt.compareWithPVlogMappedFile	SystemVerilog	Compares the current file with its PVerilog preprocessed/generated file.
Show Associated Getters in Config DB View	dvt.ConfigDBView.showAssociatedGetters	SystemVerilog	Shows the getters associated with the selected Config DB element.
Show Associated Setter in Config DB View	dvt.ConfigDBView.showAssociatedSetter	SystemVerilog	Shows the setter associated with the selected Config DB element.
Show in Config DB View	dvt.ConfigDBView.showInConfigDBView	SystemVerilog	Reveals the selected set or get call in the Config DB View.
Override Constraints…	dvt.contentAssist.getAllOverrideConstraints	SystemVerilog	Opens a dialog to select inherited constraints and inserts them in the current class at the cursor position. The overridden constraints can be inserted either as a full body inside the class, or split into an extern prototype inside the class and the actual implementation outside the class body.
Override Methods…	dvt.contentAssist.getAllOverrideMethods	SystemVerilog, e Language	Opens a dialog to select inherited methods and inserts them in the current class at the cursor position. The overridden methods can be inserted either as a full body inside the class, or split into an extern prototype inside the class and the actual implementation outside the class body.
Generate Getters and Setters…	dvt.contentAssist.getAllSettersGetters	SystemVerilog	Opens a dialog to select setters and getters and inserts them in the current class at the cursor position.
Copy Design Breadcrumb Hierarchy Path	dvt.copyDesignHierarchyPath	SystemVerilog, VHDL	Copies the design breadcrumb hierarchy path to the clipboard.
Copy Qualified Name	dvt.copyQualifiedName	SystemVerilog, VHDL, e Language	Copies the fully qualified name of the selected element to the clipboard.
Copy Verification Breadcrumb Hierarchy Path	dvt.copyVerificationHierarchyPath	SystemVerilog, e Language	Copies the verification breadcrumb hierarchy path to the clipboard.
Deactivate	dvt.deactivate.force	All	Disables DVT support for the current workspace.
Breakpoint Properties…	dvt.debug.breakpointProperties	SystemVerilog	Opens the breakpoint properties dialog to configure breakpoint settings.
Extension Host Heap Snapshot	dvt.debug.extensionHostHeapSnapshot	All	Takes a heap snapshot of the extension host process for debugging memory issues.
Design Breadcrumb Navigation…	dvt.designBreadcrumbNavigation	SystemVerilog, VHDL	Opens a quick pick that allows design breadcrumb navigation.
Show Design Hierarchy	dvt.designHierarchy.showDesignHierarchy	SystemVerilog, VHDL	Opens Design Hierarchy View with the design element under the cursor set as the top of the hierarchy.
Copy All Diagnostics	dvt.diagnostics.copyAll	All	Copies all diagnostics from the Diagnostics View to the clipboard.
Disable Diagnostics Auto Refresh	dvt.diagnostics.disableAutoRefresh	All	Disables the auto refresh of the Diagnostics View.
Enable Diagnostics Auto Refresh	dvt.diagnostics.enableAutoRefresh	All	Enables the auto refresh of the Diagnostics View.
Start Thread Dump Collector	dvt.diagnostics.startThreadDumpCollector	All	Starts the thread dump collector for diagnosing performance issues.
Stop Thread Dump Collector	dvt.diagnostics.stopThreadDumpCollector	All	Stops the thread dump collector.
Disable Sorting Config DB View By Execution	dvt.disableSortByExecutionConfigDB	SystemVerilog	Disables sorting the Config DB View by execution order.
Display Registers as List in Registers View	dvt.displayRegistersAsList	SystemVerilog	Displays registers as a flat list in the Registers View.
Display Registers as Tree in Registers View	dvt.displayRegistersAsTree	SystemVerilog	Displays registers as a tree in the Registers View.
Generate DPI-C Headers	dvt.dpic.generateStubs	SystemVerilog	Generates DPI-C header files for the selected DPI-C functions.
Enable Sorting Config DB View By Execution	dvt.enableSortByExecutionConfigDB	SystemVerilog	Enables sorting the Config DB View by execution order.
Expand All Macros	dvt.expandAll	SystemVerilog	Expands all macros from the current file in a new file.
Expand Compile Order	dvt.expandAllCompileOrder	All	Expands all items in the Compile Order View. See Compile Order View.
Expand Config DB	dvt.expandAllConfigDB	SystemVerilog	Expands all items in the Config DB View.
Expand Design Hierarchy	dvt.expandAllDesignHierarchy	SystemVerilog, VHDL	Expands all items in the Design Hierarchy View.
Expand Factory Overrides	dvt.expandAllFactoryOverrides	SystemVerilog	Expands all items in the Factory Overrides View.
Expand All Macros Inline	dvt.expandAllInline	SystemVerilog	Expands all macros from the current file inline.
Expand Macro All Levels	dvt.expandAllLevels	SystemVerilog, e Language	Expands the selected macro all levels in a new file.
Expand Macro All Levels Inline	dvt.expandAllLevelsInline	SystemVerilog, e Language	Expands the selected macro all levels inline in the editor.
Expand Registers	dvt.expandAllRegisters	SystemVerilog	Expands all items in the Registers View.
Expand Verification Hierarchy	dvt.expandAllVerificationHierarchy	SystemVerilog, e Language	Expands all items in the Verification Hierarchy View.
Expand Macro One Level	dvt.expandOneLevel	SystemVerilog	Expands the selected macro one level in a new file.
Expand Macro One Level Inline	dvt.expandOneLevelInline	SystemVerilog	Expands the selected macro one level inline in the editor.
Start Performance Exploration	dvt.exploratory.startExploration.conf	SystemVerilog, VHDL	Starts a performance exploration session for the selected configuration.
Show in Factory Overrides View	dvt.factoryOverridesView.showInFactoryOverridesView	SystemVerilog	Reveals the selected override in the Factory Overrides View.
Filter Config DB View	dvt.filterConfigDB	SystemVerilog	Filters the items in the Config DB View.
Filter Factory Overrides View	dvt.filterFactoryOverrides	SystemVerilog	Filters the items in the Factory Overrides View.
Perform Full Design Elaboration	dvt.full.design.elaboration	SystemVerilog, VHDL	Performs a full design elaboration of the current project.
Run Garbage Collector	dvt.garbageCollector.run	All	Runs the garbage collector to free unused memory.
Hide Generates Without Instances in Design Hierarchy	dvt.hideGeneratesDesignHierarchy	SystemVerilog, VHDL	Hides generate blocks that have no instances in the Design Hierarchy View.
Go to Architecture Declaration	dvt.hyperlinks.architectureDeclaration	SystemVerilog, VHDL	Goes to the declaration of the architecture. See Hyperlinks.
Go to Component Declaration	dvt.hyperlinks.componentDeclaration	VHDL	Goes to the declaration of the component. See Hyperlinks.
Go to Entity Declaration	dvt.hyperlinks.entityDeclaration	SystemVerilog, VHDL	Goes to the declaration of the entity. See Hyperlinks.
Jump to Assignment	dvt.hyperlinks.jumpToAssignment	SystemVerilog, VHDL	Jumps to the next assignment of the selected signal. See Hyperlinks.
Jump to Case Branch	dvt.hyperlinks.jumpToCaseBranch	SystemVerilog	Jumps to the matching case branch of the selected case item.
Jump to Matching Pair	dvt.hyperlinks.jumpToMatchingPair	All	Jumps to the matching pair of the selected delimiter.
Jump to State Machine	dvt.hyperlinks.jumpToStateMachine	VHDL	Jumps to the case branch where the element under cursor is used. See Hyperlinks.
Show Importing File	dvt.hyperlinks.openImportingFile	e Language	Shows the file that imports the selected file. See Hyperlinks.
Show Including File	dvt.hyperlinks.openIncludingFile	SystemVerilog	Shows the file that includes the selected file.
Select to Matching Pair	dvt.hyperlinks.selectToMatchingPair	All	Selects the text up to the matching pair of the selected delimiter.
Show Connected TLM Ports	dvt.hyperlinks.showConnectedTLMPorts	SystemVerilog	Shows the connected TLM ports of the selected element. See Hyperlinks.
Show Determinant	dvt.hyperlinks.showDeterminant	e Language	Opens the determinant field declaration. See Hyperlinks.
Show First Implementation	dvt.hyperlinks.showFirstImplementation	e Language	Shows the first implementation of the selected method or event. See Hyperlinks.
Show PVerilog Preprocessed/Generated File	dvt.hyperlinks.showPVlogMappedFile	SystemVerilog	Shows the PVerilog preprocessed/generated file for the current file.
Show When Subtype	dvt.hyperlinks.showWhenSubtype	e Language	Opens the first explicit implementation of the selected layer. See Hyperlinks.
Go to Super Implementation	dvt.hyperlinks.superImplementation	SystemVerilog	Opens the implementation of the overridden method. See Hyperlinks.
Restart Language Server	dvt.languageServer.restart	All	Restarts the DVT language server.
Method Layers Collect	dvt.Layers.methodLayersCollect	e Language	Collects the method layers for the selected element.
Show Full Type Layers in Layers View	dvt.Layers.showFullTypeLayers	e Language	Shows the full type of the layers in the Layers View.
Show Layers	dvt.Layers.showLayers	e Language	Shows the layers for the selected element.
Show Subtype Layers in Layers View	dvt.Layers.showSubtypeLayers	e Language	Shows the subtype of the layers in the Layers View.
Show Subtype & Supertype Layers in Layers View	dvt.Layers.showSubtypeSupertypeLayers	e Language	Shows the subtype and supertype of the layers in the Layers View.
Show Supertype Layers in Layers View	dvt.Layers.showSupertypeLayers	e Language	Shows the supertype of the layers in the Layers View.
Open License Output	dvt.license.openLicenseOutput	All	Opens the license output panel. See Set the License.
Open With Log Viewer	dvt.logViewer.open	All	Opens the selected file with the DVT Log Viewer.
Reveal Current Log Viewer	dvt.logViewer.reveal	All	Reveals the current Log Viewer panel.
Open Verification Breadcrumb Create Call	dvt.openCreateCall	SystemVerilog	Opens the create call of the selected verification breadcrumb instance.
Open Verification Breadcrumb Field Declaration	dvt.openFieldDeclaration	SystemVerilog, e Language	Opens the field declaration of the selected verification breadcrumb instance.
Open Design Breadcrumb Instance	dvt.openInstance	SystemVerilog, VHDL	Jumps to the corresponding instance from the design breadcrumb. See Hyperlinks.
Show Bindings	dvt.references.showBindings	e Language	Shows all bound method ports of the selected port. See Hyperlinks.
Show Constraints	dvt.references.showConstraints	SystemVerilog, e Language	Shows the constraints of the selected element.
Show Emitters	dvt.references.showEmitters	e Language	Shows the emitters of the selected element.
Show Instances	dvt.references.showInstances	All	Shows the instances of the selected element.
Show Readers	dvt.references.showReaders	SystemVerilog, VHDL, e Language	Shows the readers of the selected element.
Show Writers	dvt.references.showWriters	SystemVerilog, VHDL, e Language	Shows the writers of the selected element.
Show in Registers View	dvt.registersView.showInRegistersView	SystemVerilog	Reveals the selected element in the Registers View.
Show All Files in Compile Order	dvt.restoreAllFilesCompileOrder	All	Restores all files in the Compile Order View. See Compile Order View.
Run Checkout Hook	dvt.runCheckoutHook	All	Runs the checkout hook for the current project.
Search…	dvt.search	SystemVerilog, VHDL, e Language	Opens the DVT search dialog to search for elements in the compiled files.
Select Other Design Breadcrumb Instance…	dvt.selectOtherDesignInstance	SystemVerilog, VHDL	Selects another instance in the design breadcrumb.
Select Other Verification Breadcrumb Instance…	dvt.selectOtherVerificationInstance	SystemVerilog, e Language	Selects another instance in the verification breadcrumb.
Select Design Hierarchy Top	dvt.selectTopDesignHierarchy	SystemVerilog, VHDL	Select the Design Hierarchy View top from either top modules for Verilog, or top architectures for VHDL.
Select Verification Hierarchy Top	dvt.selectTopVerificationHierarchy	SystemVerilog, e Language	Select the Verification Hierarchy View top from either UVM tests for Verilog, or top units for Elang.
Set Current Build Configuration…	dvt.setCurrentBuildConfiguration	All	Sets the current build configuration for the project. See Build Configurations.
Show All in Verification Hierarchy	dvt.showAllEnvironmentVerificationHierarchy	SystemVerilog, e Language	Shows the full environment in the Verification Hierarchy View.
Show All Files in Compile Order	dvt.showAllFilesCompileOrder	All	Shows all files in the Compile Order View. See Compile Order View.
Show Build Config in Compile Order	dvt.showBuildConfigCompileOrder	All	Shows the build config hierarchy as it results from the -f compile directives, starting from the active build configuration. See Compile Order View.
Show Diagram	dvt.showDiagram	All	Shows the design diagram for the current selection.
Show Only Files With Errors in Compile Order	dvt.showFilesWithErrorsCompileOrder	All	Shows only the files with errors in the Compile Order View.
Show Generates Without Instances in Design Hierarchy	dvt.showGeneratesDesignHierarchy	SystemVerilog, VHDL	Shows generate blocks that have no instances in the Design Hierarchy View.
Show License Log	dvt.showLicenseLog	All	Shows the license log output. See Set the License.
Show Only Components in Verification Hierarchy	dvt.showOnlyComponentsVerificationHierarchy	SystemVerilog, e Language	Shows only components in the Verification Hierarchy View.
Create New Code Snippet…	dvt.snippets.createNewSnippet	All	Creates a new code snippet from the selected code. See Code Snippets.
Disable Sorting Registers View by Address	dvt.sortByAddressOff	SystemVerilog	Disables sorting the Registers View by address.
Sort Registers View by Address	dvt.sortByAddressOn	SystemVerilog	Sorts the Registers View by address.
Toggle Content Filters	dvt.toggleContentFilters	All	See Content Filters.
UVM Field Editor	dvt.uvm.fieldEditor	SystemVerilog	Opens the UVM Field Editor for the selected class.
Print UVM Runtime Stack Trace	dvt.uvm.runtime.print.stacktrace	SystemVerilog	Prints the UVM runtime stack trace to the console.
Verification Breadcrumb Navigation…	dvt.verificationBreadcrumbNavigation	SystemVerilog, e Language	Opens a quick pick that allows verification breadcrumb navigation.
Show Verification Hierarchy	dvt.verificationHierarchy.showVerificationHierarchy	SystemVerilog, e Language	Opens Verification Hierarchy View with the verification element under the cursor set as the top of the hierarchy.
Reapply Waivers	dvt.waivers.reapply	All	Reapplies all compile waivers. See Compile Waivers.
Create New Waiver…	dvt.waivers.showWizard	All	Opens the wizard to create a new compile waiver. See Compile Waivers.
Waveform Viewer	dvt.wave.viewer	All	Opens the Waveform Viewer.

DVT AI

Command Name	Command ID	Natures	Description
Start a New Chat Session	dvt.ai.chat.openNewSession	All	Start an empty chat session.
Save Chat Session as Blueprint	dvt.ai.chat.saveSessionAsBlueprint	All	Saves the current chat session as a reusable blueprint.
Show Last Chat Session	dvt.ai.chat.showConversation	All	Shows the last DVT AI chat session.
Show Chat History	dvt.ai.chat.showHistory	All	Shows the DVT AI chat history.
Create New Blueprint	dvt.ai.createNewBlueprint	All	Create a blueprint from scratch.
Create New Profile	dvt.ai.createNewProfile	All	Create a profile from scratch.
Create New Prompt Snippet	dvt.ai.createNewPromptSnippet	All	Create a prompt snippet from scratch.
Edit Code Completion Blueprint	dvt.ai.editCodeCompletionBlueprint	All	Create a custom Code Completion blueprint, offering the ability to customize the prompt that is sent to the LLM.
Edit Predefined Blueprint	dvt.ai.editPredefinedBlueprint	All	Customize the behavior of a predefined blueprint.
Edit Predefined Profile	dvt.ai.editPredefinedProfile	All	Customize the behavior of a predefined profile.
Edit Predefined Prompt Snippet	dvt.ai.editPredefinedPromptSnippet	All	Customize the behavior of a predefined prompt snippet.
Open Protect File	dvt.ai.openProtectFile	All	Open the AI protect file.
Create New Problem Auto-correct Blueprint	dvt.ai.problems.createNewProblemAutocorrectBlueprint	All	Create a new problem auto-correct blueprint from scratch.
Run Last Session in Chat	dvt.ai.runLastSessionInChat	All	Rerun the last session only in chat, regardless of where it ran previously.
Send File to Prompt	dvt.ai.sendFileToPrompt	All	Focus the AI chat prompt and insert the current file as a symbol (e.g. #file:<filename>).
Send Selected Lines to Prompt as Anchor	dvt.ai.sendSelectedLinesToPromptAsAnchor	All	Focus the AI chat prompt and insert the currently selected lines. The selected lines will be inserted as a symbol (e.g. #file:<filename>:<startLine>-<endLine>). If the file content changes from the command invocation until the prompt is sent to the LLM, the symbol expansion will include the updated content.
Send Selected Lines to Prompt as Code Block	dvt.ai.sendSelectedLinesToPromptAsCodeBlock	All	Focus the AI chat prompt and insert the currently selected lines. The selected lines will be inserted as a code block surrounded by ``` delimiters.
Set Language Model	dvt.ai.setCurrentLanguageModel	All	Set the default LLM that will be used from now on for new sessions.
Configure Agent Skills…	dvt.ai.skills.configureAgentSkills	All	Create a new agent skill from template or generate one using AI.
Start a New Session from Blueprint	dvt.ai.startNewSessionFromBlueprint	All	List all the built-in and custom blueprints. The selected blueprint will start a new session.
Trigger Code Completion	dvt.ai.triggerCodeCompletion	All	Trigger the AI Code Completion.
Update Language Model Configuration	dvt.ai.updateLanguageModelConfiguration	All	Recomputes and updates the language model configuration.
Update Model Information	dvt.ai.updateModelInformation	All	Update the built-in database for model context window and cost information.
Create New Verissimo Auto-correct Blueprint	dvt.ai.verissimo.createNewVerissimoAutocorrectBlueprint	All	Creates a new DVT AI blueprint for Verissimo auto-correction.

DVT AI Blueprint

Command Name	Command ID	Natures	Description
Analyze Root Cause of Current Test Failure	dvt.ai.analyzeRootCauseOfTestFailure	All	Asks the LLM to find the root cause of a test failure, based on the current log file and waveform viewer.
Add Logging to the Selected Code	dvt.ai.editor.addLoggingToSelectedCode	All	Instructs the LLM to add logging statements to the selected code.
Explain the Selected Assertion	dvt.ai.editor.describeSelectedAssertion	All	Instructs the LLM to explain the selected assertion in a concise manner, including WaveDrom diagrams for pass and fail scenarios.The user request defined by the blueprint and the LLM reply appear in the chat. You can change the request, regenerate the reply or continue the conversation
Explain the Selected Code	dvt.ai.editor.describeSelectedCode	All	Instructs the LLM to explain the selected code in a concise manner. The user request defined by the blueprint and the LLM reply appear in the chat. You can change the request, regenerate the reply or continue the conversation.
Analyze and Fix the Selected Code	dvt.ai.editor.fixSelectedCode	All	Instructs the LLM to find and fix any problems identified in the selected code.
Generate convert2string for the Current Class	dvt.ai.editor.generateConvert2stringFunction	All	Instructs the LLM to generate the convert2string function in the class at the current cursor position.
Generate Coverage for the Current Class	dvt.ai.editor.generateCoverageForCurrentClass	All	Instructs the LLM to generate coverage in the form of covergroups in the class at the current cursor position.
Improve the Selected Code	dvt.ai.editor.improveSelectedCode	All	Instructs the LLM to suggest and apply improvements for the selected code.
Interconnect RTL Based on Opened Spec	dvt.ai.editor.interconnectRTLBasedOnSpec	All	Instructs the LLM to interconnect, or review and update the interconnections in a module based on the opened documentation file. The LLM can request additional information and report its progress in the chat. Tools are used to obtain additional information or to edit the code.
Add Comment to the Selected Code	dvt.ai.editor.writeCommentsForSelectedElement	All	Instructs the LLM to add comments for an element (e.g. module, class) or a section of code.
Review Uncommitted Changes	dvt.ai.git.codeReview	All	Asks the LLM to code review all of your tracked changes. The user request defined by the blueprint and the LLM reply appear in the chat. You can change the request, regenerate the reply or continue the conversation.
Generate Commit Message	dvt.ai.git.generateChatCommitMessage	All	Asks the LLM to generate an adequate commit message for the currently staged changes. The user request defined by the blueprint and the LLM reply appear in the chat. You can change the request, regenerate the reply or continue the conversation.
Summarize Remote Changes Ahead of Current Commit	dvt.ai.git.summarizeRemoteChanges	All	Asks the LLM to summarize the remote changes ahead of the local HEAD. The user request defined by the blueprint and the LLM reply appear in the chat. You can change the request, regenerate the reply or continue the conversation.

DVT MCP

Command Name	Command ID	Natures	Description
Install Agent Skills	dvt.ai.skills.installAgentSkills	All	Trigger the DVT Agent Skills installation.

DVT Waveform Viewer

Command Name	Command ID	Natures	Description
All Signals	dvt.wave.addAllSignals	SystemVerilog, VHDL	Adds all signals of the selected scope to the Waveform Viewer.
Ports	dvt.wave.addPorts	SystemVerilog, VHDL	Adds all ports of the selected scope to the Waveform Viewer.
Signal	dvt.wave.addToWaveViewer	SystemVerilog, VHDL	Adds the selected signal to the Waveform Viewer.
With Drivers	dvt.wave.addWithDrivers	SystemVerilog, VHDL	Adds the selected signal and its drivers to the Waveform Viewer.
With Loads	dvt.wave.addWithLoads	SystemVerilog, VHDL	Adds the selected signal and its loads to the Waveform Viewer.
Reveal Current Waveform	dvt.wave.revealCurrentWave	All	Reveals the current waveform in the Waveform Viewer.
Reveal	dvt.wave.revealInWaveViewer	SystemVerilog, VHDL	Brings the current waveform in focus, scrolls to the selected port and selects it.
Create WaveDrom Diagram	dvt.wave.waveformViewerCreateWaveDromDiagram	SystemVerilog, VHDL	Creates a WaveDrom timing diagram from the selected signals.
Zoom To Fit Times	dvt.wave.zoomToFitTimes	All	Zooms the Waveform Viewer to fit the specified time range.

Specador

Command Name	Command ID	Natures	Description
Edit Preferences	dvt.specador.editPreferences	All	Edits a chosen Specador XML preference file.
Generate Documentation	dvt.specador.generateDocumentation	All	Allows customizing the preferences and generates Specador documentation for the current project.
Generate Markdown File	dvt.specador.generateMarkdownFile	SystemVerilog, VHDL, e Language	Generates a Markdown template file for all elements in the current file, to be used with Specador.
Set Preview Preferences	dvt.specador.setPreviewPreferences	All	Sets the Specador HTML Preview preferences.
Show in HTML Preview	dvt.specador.showLivePreview	SystemVerilog, VHDL, e Language	Shows the preview of the HTML Specador documentation for the current element.

Verissimo

Command Name	Command ID	Natures	Description
Clear Linting Results	dvt.verissimo.clearProblems	All	Clears all Verissimo linting results from the Problems View.
Generate…	dvt.verissimo.generate	All	Generates XML or HTML documentation files for specified rulesets.
Lint Project…	dvt.verissimo.lint	All	Runs the Verissimo linter on the entire project.
Lint File…	dvt.verissimo.lintFile	All	Runs the Verissimo linter on the selected file.
Lint File With Last Configuration	dvt.verissimo.lintFileWithLastConfiguration	All	Lints the selected file using the last Verissimo linting configuration.
Ruleset Editor…	dvt.verissimo.openRulesetEditor	All	Opens the Verissimo ruleset editor.