Ibex: An embedded 32 bit RISC-V CPU core
Note
This documentation is generated from the Ibex RISC-V Core official repository, to illustrate Specador Documentation Generator functionalities:
Support for UML Diagrams: Class csr_base_seq
Support for UVM Component Diagrams for uvm_test: Class core_ibex_directed_test
Support for Bitfields Diagrams for packed structs: Package prim_secded_pkg
Support for Finite State Machine Diagrams: Module ibex_controller
Ibex is a production-quality open source 32 bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs.
You are now reading the Ibex documentation. The documentation is split into four parts.
The Overview documentation looks at Ibex from high up. It answers questions like what are the high-level properties of Ibex, which standards is Ibex following, and where is it typically used.
The User Guide provides all necessary information to use Ibex. It is aimed at hardware developers integrating Ibex into a design, and software developers writing software running on Ibex.
The Reference Guide provides background information. It describes the design in detail, discusses the verification approach and the resulting testbench structures, and generally helps to understand Ibex in depth.
The Developer Guide is aimed at people making changes to Ibex itself. Since Ibex is open source, every user of Ibex is encouraged to learn how to adapt Ibex to their use case, and be part of the open development process.