Interface clk_rst_if

clk_rst_if #( .IfName(IfName) ) u_clk_rst_if ( .clk(clk), .rst_n(rst_n) );

Block Diagram of clk_rst_if

Interface

clk_rst_if

Generic clock and reset interface for clock events in various utilities It also generates o_clk and o_rst_n signals for driving clk and rst_n in the tb. The advantage is clk and rst_n can be completely controlled in course of the simulation. This interface provides methods to set freq/period, wait for clk/rst_n, apply rst_n among other things. See individual method descriptions below. inout clk inout rst_n

Parameters

Name	Default value	Description
IfName	"main"

Ports

Name	Type	Direction	Description
clk	wire logic	inout
rst_n	wire logic	inout

Signals

Name	Type	Description
drive_clk	bit	Enables clock to be generated and driven by this interface.
o_clk	logic	The internal output clock value.
drive_rst_n	bit	Enables the rst_n to be generated and driven by this interface.
o_rst_n	logic	The internal output reset value.
clk_gate	bit	Applies clock gating.
clk_period_ps	int	The nominal (chosen) frequency (as period in ps) of the driven clock (50MHz by default).
clk_freq_scaling_pc	int	The variation of clock period (mimics uncalibrated clocks), to scale the nominal frequency down. If set to non-zero value, the clock frequency is scaled randomly on every edge.
clk_freq_scaling_chance_pc	int	The percentage chance of freq scaled down randomly on each edge.
clk_freq_scale_up	bit	Clock frequency is scaled down. This enables the frequency to be randomly scaled up as well. Note If set, the randomness of the clock frequency being scaled up or down may result in a bigger frequency distribution than the intended clk_freq_scaling_pc setting. For example, 50MHz with 10% scaling may result in pulses that are < 45MHz and > 55MHz wide as well.
clk_freq_mhz	real	The computed clock frequency in MHz.
duty_cycle	int	The duty cycle of the clock period as percentage. If jitter and scaling is applied, then the duty cycle will not be maintained.
max_plus_jitter_ps	int	Maximum jitter applied to each period of the clock this is expected to be about 20% or less than the clock period. The jitter is divided to two values plus-jitter and minus-jitter. Plus jitter is the possible time can be added to the clock period, while the minus jittter is the possible time can be subtracted from the clock period. _:| : : |:___ The actual jitter value is picked randomly within the window {[-max_minus_jitter_ps:max_plus_jitter_ps]} and is added to the time to next edge.
max_minus_jitter_ps	int
jitter_chance_pc	int	The percentage chance of jitter occurring on each edge. If 0 (default value), then jitter is disabled altogether. If 100, jitter is computed and applied at every edge.
recompute	bit	Internal signal indicating the clock half periods need to be recomputed.
clk_hi_ps	int	Internal signal indicating the amount of time for which the clock stays high / lo in the next cycle.
clk_lo_ps	int
clk_hi_modified_ps	real
clk_lo_modified_ps	real
sole_clock	bit	If true, this is the only clock in the system; there is no need to add initial jitter.
msg_id	string	use IfName as a part of msgs to indicate which clk_rst_vif instance

Events

set_active_called

This event is used to start the initial block driving the clock after set_active sets the values of drive_clk and drive_rst_n.

Functions

function void

set_freq_khz(int freq_khz)

set the clk frequency in khz

Parameters:

freq_khz (int)

function void

set_freq_mhz(int freq_mhz)

set the clk frequency in mhz

Parameters:

freq_mhz (int)

function void

set_freq_scaling(int freq_scaling_pc, int freq_scaling_chance_pc = 50, bit freq_scale_up = 1'b0)

Set the clk frequency scaling, chance in percentage and scaling up.

freq_scaling_pc is a positive integer that determines by what amount (as percentage of the nominal frequency) is the frequency scaled (jittered) down. freq_scaling_chance_pc is a percentage number between 0 and 100 that determines how often is the scaling randomly recomputed and applied. freq_scale_up is a bit that enables the random scaling up of the frequency as well.

Parameters:

• freq_scaling_pc (int)

• freq_scaling_chance_pc (int)

• freq_scale_up (bit)

function void

set_active(bit drive_clk_val = 1'b1, bit drive_rst_n_val = 1'b1)

Enables the clock and reset to be driven.

Parameters:

• drive_clk_val (bit)

• drive_rst_n_val (bit)

function void

set_period_ps(int period_ps)

set the clk period in ps

Parameters:

period_ps (int)

function void

set_duty_cycle(int duty)

set the duty cycle (1-99)

Parameters:

duty (int)

function void

set_max_jitter_ps(int plus_jitter_ps, int minus_jitter_ps = plus_jitter_ps)

set maximum jitter in ps, separating the plus jitter and the minus jitter. In default the plus and minus jitters are the same.

Parameters:

• plus_jitter_ps (int)

• minus_jitter_ps (int)

function void

set_jitter_chance_pc(int jitter_chance)

set jitter chance in percentage (0

0

dont add any jitter; 100 - add jitter on every clock edge

Parameters:

jitter_chance (int)

function void

set_sole_clock(bit is_sole = 1'b1)

Set whether this is the only clock in the system. If true, various bits of timing randomisation are disabled. If there's no other clock to (de)synchronise with, this should not weaken the test at all.

Parameters:

is_sole (bit)

function void

stop_clk()

stop / gate the clk

function void

apply_freq_scaling()

Scales the clock frequency up and down on every edge.

function void

apply_jitter()

Applies jitter to clk_hi and clk_lo half periods based on jitter_chance_pc.

Tasks

function

wait_clks(int num_clks)

Wait for 'n' clocks based of postive clock edge

Parameters:

num_clks (int)

function

wait_n_clks(int num_clks)

Wait for 'n' clocks based of negative clock edge

Parameters:

num_clks (int)

function

wait_clks_or_rst(int num_clks)

Wait for 'num_clks' clocks based on the positive clock edge or reset, whichever comes first.

Parameters:

num_clks (int)

function

wait_for_reset(bit wait_negedge = 1'b1, bit wait_posedge = 1'b1)

wait for rst_n to assert and then deassert

Parameters:

• wait_negedge (bit)

• wait_posedge (bit)

function

start_clk(bit wait_for_posedge = 1'b0)

start / ungate the clk

Parameters:

wait_for_posedge (bit)

function

drive_rst_pin(logic val = 1'b0)

can be used to override clk/rst pins, e.g. at the beginning of the simulation

Parameters:

val (logic)

function

apply_reset(int pre_reset_dly_clks = 0, int reset_width_clks = $urandom_range(50, 100), int post_reset_dly_clks = 0, rst_scheme_e rst_n_scheme = RstAssertAsyncDeassertSync)

apply reset with specified scheme Note: for power on reset, please ensure pre_reset_dly_clks is set to 0

Parameters:

• pre_reset_dly_clks (int)

• reset_width_clks (int)

• post_reset_dly_clks (int)

• rst_n_scheme (rst_scheme_e)

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