[source]

Module ibex_compressed_decoder

clk_ilogicrst_nilogicvalid_ilogicinstr_i[31:0]logicinstr_ologic[31:0]is_compressed_ologicillegal_instr_ologic

Block Diagram of ibex_compressed_decoder

Ports

Name

Type

Direction

Description

clk_i

wire logic

input

rst_ni

wire logic

input

valid_i

wire logic

input

instr_i

wire logic [31 : 0]

input

instr_o

var logic [31 : 0]

output

is_compressed_o

var logic

output

illegal_instr_o

var logic

output

Assertions

Name

Kind

Description

ibex_compressed_decoder.IbexInstrValidKnown

concurent assert

The valid_i signal used to gate below assertions must be known.

disable iff((!rst_ni)!=='0)! $isunknown(valid_i)

ibex_compressed_decoder.IbexInstrLSBsKnown

concurent assert

Selectors must be known/valid.

disable iff((!rst_ni)!=='0)(valid_i |-> ! $isunknown(instr_i[1 : 0]))

ibex_compressed_decoder.IbexC0Known1

concurent assert

disable iff((!rst_ni)!=='0)((valid_i && (instr_i[1 : 0] == 2'b00)) |-> ! $isunknown(instr_i[15 : 13]))

ibex_compressed_decoder.IbexC1Known1

concurent assert

disable iff((!rst_ni)!=='0)((valid_i && (instr_i[1 : 0] == 2'b01)) |-> ! $isunknown(instr_i[15 : 13]))

ibex_compressed_decoder.IbexC1Known2

concurent assert

disable iff((!rst_ni)!=='0)(((valid_i && (instr_i[1 : 0] == 2'b01)) && (instr_i[15 : 13] == 3'b100)) |-> ! $isunknown(instr_i[11 : 10]))

ibex_compressed_decoder.IbexC1Known3

concurent assert

disable iff((!rst_ni)!=='0)((((valid_i && (instr_i[1 : 0] == 2'b01)) && (instr_i[15 : 13] == 3'b100)) && (instr_i[11 : 10] == 2'b11)) |-> ! $isunknown({instr_i[12], instr_i[6 : 5]}))

ibex_compressed_decoder.IbexC2Known1

concurent assert

disable iff((!rst_ni)!=='0)((valid_i && (instr_i[1 : 0] == 2'b10)) |-> ! $isunknown(instr_i[15 : 13]))

Always Blocks

always_comb @()

////////////////////// Compressed decoder // //////////////////////

Instances