Module prim_ram_1p_adv

prim_ram_1p_adv #( .Depth(Depth), .Width(Width), .DataBitsPerMask(DataBitsPerMask), .MemInitFile(MemInitFile), .EnableECC(EnableECC), .EnableParity(EnableParity), .EnableInputPipeline(EnableInputPipeline), .EnableOutputPipeline(EnableOutputPipeline), .HammingECC(HammingECC) ) u_prim_ram_1p_adv ( .clk_i(clk_i), .rst_ni(rst_ni), .req_i(req_i), .write_i(write_i), .addr_i(addr_i), .wdata_i(wdata_i), .wmask_i(wmask_i), .rdata_o(rdata_o), .rvalid_o(rvalid_o), .rerror_o(rerror_o), .cfg_i(cfg_i), .alert_o(alert_o) );

Block Diagram of prim_ram_1p_adv

Single-Port SRAM Wrapper

Supported configurations

• ECC for 32b and 64b wide memories with no write mask (Width == 32 or Width == 64, DataBitsPerMask is ignored).

• Byte parity if Width is a multiple of 8 bit and write masks have Byte granularity (DataBitsPerMask == 8).

Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write mask cannot be used and has to be tied to {Width{1'b1}}.

Parameters

Name	Default	Description
Depth	512
Width	32
DataBitsPerMask	1	Number of data bits per bit of write mask
MemInitFile	""	VMEM file to initialize the memory with
EnableECC	0	Configurations Enables per-word ECC
EnableParity	0	Enables per-Byte Parity
EnableInputPipeline	0	Adds an input register (read latency +1)
EnableOutputPipeline	0	Adds an output register (read latency +1)
HammingECC	0	This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC. It is recommended to leave this parameter at its default setting (HSIAO), since this results in a more compact and faster implementation.

Ports

Name	Type	Direction	Description
clk_i	wire logic	input
rst_ni	wire logic	input
req_i	wire logic	input
write_i	wire logic	input
addr_i	wire logic [Aw - 1 : 0]	input
wdata_i	wire logic [Width - 1 : 0]	input
wmask_i	wire logic [Width - 1 : 0]	input
rdata_o	var logic [Width - 1 : 0]	output
rvalid_o	var logic	output	read response (rdata_o) is valid
rerror_o	var logic [1 : 0]	output	Bit1 Uncorrectable, Bit0: Correctable
cfg_i	wire ram_1p_cfg_t	input	config
alert_o	var logic	output	When detecting multi-bit encoding errors, raise alert.

Assertions

Name	Kind	Description
prim_ram_1p_adv.CannotHaveEccAndParity_A	immediate assert	! (EnableParity && EnableECC)
prim_ram_1p_adv.SecDecWidth_A	immediate assert	check supported widths (Width inside {16, 32})
prim_ram_1p_adv.OnlyWordWritePossibleWithEccPortA_A	concurent assert	the wmask is constantly set to 1 in this case disable iff((!rst_ni)!=='0)(req_i |-> (wmask_i == {Width{1'b1}}))
prim_ram_1p_adv.WidthNeedsToBeByteAligned_A	immediate assert	((Width % 8) == 0)
prim_ram_1p_adv.ParityNeedsByteWriteMask_A	immediate assert	(DataBitsPerMask == 8)

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