[source]

Module ibex_decoder

RV32ERV32MRV32BBranchTargetALUclk_ilogicrst_nilogicbranch_taken_ilogicinstr_first_cycle_ilogicinstr_rdata_i[31:0]logicinstr_rdata_alu_i[31:0]logicillegal_c_insn_ilogicillegal_insn_ologicebrk_insn_ologicmret_insn_ologicdret_insn_ologicecall_insn_ologicwfi_insn_ologicjump_set_ologicicache_inval_ologicimm_a_mux_sel_oibex_pkg::imm_a_sel_eimm_b_mux_sel_oibex_pkg::imm_b_sel_ebt_a_mux_sel_oibex_pkg::op_a_sel_ebt_b_mux_sel_oibex_pkg::imm_b_sel_eimm_i_type_ologic[31:0]imm_s_type_ologic[31:0]imm_b_type_ologic[31:0]imm_u_type_ologic[31:0]imm_j_type_ologic[31:0]zimm_rs1_type_ologic[31:0]rf_wdata_sel_oibex_pkg::rf_wd_sel_erf_we_ologicrf_raddr_a_ologic[4:0]rf_raddr_b_ologic[4:0]rf_waddr_ologic[4:0]rf_ren_a_ologicrf_ren_b_ologicalu_operator_oibex_pkg::alu_op_ealu_op_a_mux_sel_oibex_pkg::op_a_sel_ealu_op_b_mux_sel_oibex_pkg::op_b_sel_ealu_multicycle_ologicmult_en_ologicdiv_en_ologicmult_sel_ologicdiv_sel_ologicmultdiv_operator_oibex_pkg::md_op_emultdiv_signed_mode_ologic[1:0]csr_access_ologiccsr_op_oibex_pkg::csr_op_ecsr_addr_oibex_pkg::csr_num_edata_req_ologicdata_we_ologicdata_type_ologic[1:0]data_sign_extension_ologicjump_in_dec_ologicbranch_in_dec_ologic

Block Diagram of ibex_decoder

Parameters

Name

Default

Description
RV32E

0
RV32M

ibex_pkg::RV32MFast
RV32B

ibex_pkg::RV32BNone
BranchTargetALU

0
Ports

Name

Type

Direction

Description
clk_i

wire logic

input
rst_ni

wire logic

input
illegal_insn_o

var logic

output

to/from controller illegal instr encountered
ebrk_insn_o

var logic

output

trap instr encountered
mret_insn_o

var logic

output

return from exception instr
dret_insn_o

var logic

output

encountered return from debug instr encountered
ecall_insn_o

var logic

output

syscall instr encountered
wfi_insn_o

var logic

output

wait for interrupt instr encountered
jump_set_o

var logic

output

jump taken set signal
branch_taken_i

wire logic

input

registered branch decision
icache_inval_o

var logic

output
instr_first_cycle_i

wire logic

input

from IF-ID pipeline register instruction read is in its first cycle
instr_rdata_i

wire logic [31 : 0]

input

instruction read from memory/cache
instr_rdata_alu_i

wire logic [31 : 0]

input

instruction read from memory/cache
illegal_c_insn_i

wire logic

input

replicated to ease fan-out) compressed instruction decode failed
imm_a_mux_sel_o

var ibex_pkg::imm_a_sel_e

output

immediates immediate selection for operand a
imm_b_mux_sel_o

var ibex_pkg::imm_b_sel_e

output

immediate selection for operand b
bt_a_mux_sel_o

var ibex_pkg::op_a_sel_e

output

branch target selection operand a
bt_b_mux_sel_o

var ibex_pkg::imm_b_sel_e

output

branch target selection operand b
imm_i_type_o

var logic [31 : 0]

output
imm_s_type_o

var logic [31 : 0]

output
imm_b_type_o

var logic [31 : 0]

output
imm_u_type_o

var logic [31 : 0]

output
imm_j_type_o

var logic [31 : 0]

output
zimm_rs1_type_o

var logic [31 : 0]

output
rf_wdata_sel_o

var ibex_pkg::rf_wd_sel_e

output

register file RF write data selection
rf_we_o

var logic

output

write enable for regfile
rf_raddr_a_o

var logic [4 : 0]

output
rf_raddr_b_o

var logic [4 : 0]

output
rf_waddr_o

var logic [4 : 0]

output
rf_ren_a_o

var logic

output

Instruction reads from RF addr A
rf_ren_b_o

var logic

output

Instruction reads from RF addr B
alu_operator_o

var ibex_pkg::alu_op_e

output

ALU ALU operation selection
alu_op_a_mux_sel_o

var ibex_pkg::op_a_sel_e

output

operand a selection

reg value, PC,

alu_op_b_mux_sel_o

var ibex_pkg::op_b_sel_e

output

immediate or zero operand b selection: reg value or
alu_multicycle_o

var logic

output

immediate ternary bitmanip instruction
mult_en_o

var logic

output

MULT & DIV perform integer multiplication
div_en_o

var logic

output

perform integer division or remainder
mult_sel_o

var logic

output

as above but static, for data muxes
div_sel_o

var logic

output

as above but static, for data muxes
multdiv_operator_o

var ibex_pkg::md_op_e

output
multdiv_signed_mode_o

var logic [1 : 0]

output
csr_access_o

var logic

output

CSRs access to CSR
csr_op_o

var ibex_pkg::csr_op_e

output

operation to perform on CSR
csr_addr_o

var ibex_pkg::csr_num_e

output

CSR address
data_req_o

var logic

output

LSU start transaction to data memory
data_we_o

var logic

output

write enable
data_type_o

var logic [1 : 0]

output

size of transaction

byte, half

data_sign_extension_o

var logic

output

word or word sign extension for data read from
jump_in_dec_o

var logic

output

jump/branches jump is being calculated in ALU
branch_in_dec_o

var logic

output
Assertions

Name

Kind

Description

ibex_decoder.IbexRegImmAluOpKnown

concurent assert

Selectors must be known/valid.

disable iff((!rst_ni)!=='0)((opcode == OPCODE_OP_IMM) |-> ! $isunknown(instr[14 : 12]))

Always Blocks

always_comb @()

///////////////////// CSR operand check // /////////////////////

always_comb @()

/////////// Decoder // ///////////

always_comb @()

/////////////////////////// Decoder for ALU control // ///////////////////////////

Instances

Submodules

  • ibex_decoder

    • gen_no_rs3_flop : [if !(RV32B!=RV32BNone)]

    • gen_rv32e_reg_check_inactive : [if !(RV32E)]