Module ibex_register_file_ff

ibex_register_file_ff #( .RV32E(RV32E), .DataWidth(DataWidth), .DummyInstructions(DummyInstructions), .WrenCheck(WrenCheck), .RdataMuxCheck(RdataMuxCheck), .WordZeroVal(WordZeroVal) ) u_ibex_register_file_ff ( .clk_i(clk_i), .rst_ni(rst_ni), .test_en_i(test_en_i), .dummy_instr_id_i(dummy_instr_id_i), .dummy_instr_wb_i(dummy_instr_wb_i), .raddr_a_i(raddr_a_i), .rdata_a_o(rdata_a_o), .raddr_b_i(raddr_b_i), .rdata_b_o(rdata_b_o), .waddr_a_i(waddr_a_i), .wdata_a_i(wdata_a_i), .we_a_i(we_a_i), .err_o(err_o) );

Block Diagram of ibex_register_file_ff

RISC-V register file

Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0. This register file is based on flip flops. Use this register file when targeting FPGA synthesis or Verilator simulation.

Parameters

Name	Default	Description
RV32E	0
DataWidth	32
DummyInstructions	0
WrenCheck	0
RdataMuxCheck	0
WordZeroVal	'0

Ports

Name	Type	Direction	Description
clk_i	wire logic	input	Clock and Reset
rst_ni	wire logic	input
test_en_i	wire logic	input
dummy_instr_id_i	wire logic	input
dummy_instr_wb_i	wire logic	input
raddr_a_i	wire logic [4 : 0]	input	Read port R1
rdata_a_o	var logic [DataWidth - 1 : 0]	output
raddr_b_i	wire logic [4 : 0]	input	Read port R2
rdata_b_o	var logic [DataWidth - 1 : 0]	output
waddr_a_i	wire logic [4 : 0]	input	Write port W1
wdata_a_i	wire logic [DataWidth - 1 : 0]	input
we_a_i	wire logic	input
err_o	var logic	output	This indicates whether spurious WE or non-one-hot encoded raddr are detected.

Instances

• ibex_top : ibex_top

  • gen_regfile_ff : []

    • register_file_i : ibex_register_file_ff

Submodules

• ibex_register_file_ff

  • g_normal_r0 : [if !(DummyInstructions)]

  • g_rf_flops : [for (genvar i=1;i<NUM_WORDS;i++)]

  • gen_no_rdata_mux_check : [if !(RdataMuxCheck)]

  • gen_no_wren_check : [if !(WrenCheck)]

Flow Diagram of ibex_register_file_ff

Sub-Instances Diagram of ibex_register_file_ff

Schematic Diagram of ibex_register_file_ff

×