Module ibex_dummy_instr

ibex_dummy_instr #( .RndCnstLfsrSeed(RndCnstLfsrSeed), .RndCnstLfsrPerm(RndCnstLfsrPerm) ) u_ibex_dummy_instr ( .clk_i(clk_i), .rst_ni(rst_ni), .dummy_instr_en_i(dummy_instr_en_i), .dummy_instr_mask_i(dummy_instr_mask_i), .dummy_instr_seed_en_i(dummy_instr_seed_en_i), .dummy_instr_seed_i(dummy_instr_seed_i), .fetch_valid_i(fetch_valid_i), .id_in_ready_i(id_in_ready_i), .insert_dummy_instr_o(insert_dummy_instr_o), .dummy_instr_data_o(dummy_instr_data_o) );

Block Diagram of ibex_dummy_instr

SEC_CM

CTRL_FLOW.UNPREDICTABLE

Parameters

Name	Default	Description
RndCnstLfsrSeed	RndCnstLfsrSeedDefault
RndCnstLfsrPerm	RndCnstLfsrPermDefault

Ports

Name	Type	Direction	Description
clk_i	wire logic	input	Clock and reset
rst_ni	wire logic	input
dummy_instr_en_i	wire logic	input	Interface to CSRs
dummy_instr_mask_i	wire logic [2 : 0]	input
dummy_instr_seed_en_i	wire logic	input
dummy_instr_seed_i	wire logic [31 : 0]	input
fetch_valid_i	wire logic	input	Interface to IF stage
id_in_ready_i	wire logic	input
insert_dummy_instr_o	var logic	output
dummy_instr_data_o	var logic [31 : 0]	output

Structs

typedef struct lfsr_data_t

Always Blocks

always_comb @()

Encode instruction

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