[source]

Module prim_buf

Widthin_i[Width-1:0]logicout_ologic[Width-1:0]

Block Diagram of prim_buf

Abstract primitives wrapper.

This file is a stop-gap until the DV file list is generated by FuseSoC. Its contents are taken from the file which would be generated by FuseSoC. https://github.com/lowRISC/ibex/issues/893

Parameters

Name

Default

Description

Width

1

Ports

Name

Type

Direction

Description

in_i

wire logic [Width - 1 : 0]

input

out_o

var logic [Width - 1 : 0]

output

Instances

Submodules

gen_generic.u_impl_generic (prim_generic_buf) gen_generic u_fetch_enable_buf (prim_buf)

Flow Diagram of prim_buf

gen_generic.u_impl_generic (prim_generic_buf) in_i out_o gen_generic u_fetch_enable_buf (prim_buf) in_i out_o

Sub-Instances Diagram of prim_buf

gen_generic.u_impl_generic (prim_generic_buf) in_i out_o gen_generic u_fetch_enable_buf (prim_buf) in_i out_o

Schematic Diagram of prim_buf