[source]

Module ibex_alu

RV32Boperator_iibex_pkg::alu_op_eoperand_a_i[31:0]logicoperand_b_i[31:0]logicinstr_first_cycle_ilogicmultdiv_operand_a_i[32:0]logicmultdiv_operand_b_i[32:0]logicmultdiv_sel_ilogicimd_val_q_i[31:0]logicimd_val_d_ologic[31:0]imd_val_we_ologic[1:0]adder_result_ologic[31:0]adder_result_ext_ologic[33:0]result_ologic[31:0]comparison_result_ologicis_equal_result_ologic

Block Diagram of ibex_alu

Arithmetic logic unit

Parameters

Name

Default

Description
RV32B

ibex_pkg::RV32BNone
Ports

Name

Type

Direction

Description
operator_i

wire ibex_pkg::alu_op_e

input
operand_a_i

wire logic [31 : 0]

input
operand_b_i

wire logic [31 : 0]

input
instr_first_cycle_i

wire logic

input
multdiv_operand_a_i

wire logic [32 : 0]

input
multdiv_operand_b_i

wire logic [32 : 0]

input
multdiv_sel_i

wire logic

input
imd_val_q_i

wire logic [31 : 0]

input
imd_val_d_o

var logic [31 : 0]

output
imd_val_we_o

var logic [1 : 0]

output
adder_result_o

var logic [31 : 0]

output
adder_result_ext_o

var logic [33 : 0]

output
result_o

var logic [31 : 0]

output
comparison_result_o

var logic

output
is_equal_result_o

var logic

output

Always Blocks

always_comb @()

prepare operand a

always_comb @()

Is greater equal

always_comb @()

left shift if this is

a standard left shift (slo, sll) a rol in the first cycle a ror in the second cycle fsl: without word-swap bit: first cycle, else: second cycle fsr: without word-swap bit: second cycle, else: first cycle a single-bit instruction: bclr, bset, binv (excluding bext) bfp: bfp_mask << bfp_off

always_comb @()

shifter structure.

always_comb @()

////////////// Result mux // //////////////

Instances

Submodules

  • ibex_alu

    • g_no_alu_rvb : [if !(RV32B!=RV32BNone)]

    • gen_rev_bfp_mask : [for (genvar i=0;i<32;i++)]

    • gen_rev_operand_a : [for (genvar k=0;k<32;k++)]