Module ibex_ex_block

ibex_ex_block #( .RV32M(RV32M), .RV32B(RV32B), .BranchTargetALU(BranchTargetALU) ) u_ibex_ex_block ( .clk_i(clk_i), .rst_ni(rst_ni), .alu_operator_i(alu_operator_i), .alu_operand_a_i(alu_operand_a_i), .alu_operand_b_i(alu_operand_b_i), .alu_instr_first_cycle_i(alu_instr_first_cycle_i), .bt_a_operand_i(bt_a_operand_i), .bt_b_operand_i(bt_b_operand_i), .multdiv_operator_i(multdiv_operator_i), .mult_en_i(mult_en_i), .div_en_i(div_en_i), .mult_sel_i(mult_sel_i), .div_sel_i(div_sel_i), .multdiv_signed_mode_i(multdiv_signed_mode_i), .multdiv_operand_a_i(multdiv_operand_a_i), .multdiv_operand_b_i(multdiv_operand_b_i), .multdiv_ready_id_i(multdiv_ready_id_i), .data_ind_timing_i(data_ind_timing_i), .imd_val_we_o(imd_val_we_o), .imd_val_d_o(imd_val_d_o), .imd_val_q_i(imd_val_q_i), .alu_adder_result_ex_o(alu_adder_result_ex_o), .result_ex_o(result_ex_o), .branch_target_o(branch_target_o), .branch_decision_o(branch_decision_o), .ex_valid_o(ex_valid_o) );

Block Diagram of ibex_ex_block

Execution stage

Execution block

Hosts ALU and MUL/DIV unit

Parameters

Name	Default	Description
RV32M	ibex_pkg::RV32MFast
RV32B	ibex_pkg::RV32BNone
BranchTargetALU	0

Ports

Name	Type	Direction	Description
clk_i	wire logic	input
rst_ni	wire logic	input
alu_operator_i	wire ibex_pkg::alu_op_e	input	ALU
alu_operand_a_i	wire logic [31 : 0]	input
alu_operand_b_i	wire logic [31 : 0]	input
alu_instr_first_cycle_i	wire logic	input
bt_a_operand_i	wire logic [31 : 0]	input	Branch Target ALU All of these signals are unusued when BranchTargetALU == 0
bt_b_operand_i	wire logic [31 : 0]	input
multdiv_operator_i	wire ibex_pkg::md_op_e	input	Multiplier/Divider
mult_en_i	wire logic	input	dynamic enable signal, for FSM control
div_en_i	wire logic	input	dynamic enable signal, for FSM control
mult_sel_i	wire logic	input	static decoder output, for data muxes
div_sel_i	wire logic	input	static decoder output, for data muxes
multdiv_signed_mode_i	wire logic [1 : 0]	input
multdiv_operand_a_i	wire logic [31 : 0]	input
multdiv_operand_b_i	wire logic [31 : 0]	input
multdiv_ready_id_i	wire logic	input
data_ind_timing_i	wire logic	input
imd_val_we_o	var logic [1 : 0]	output	intermediate val reg
imd_val_d_o	var logic [33 : 0]	output
imd_val_q_i	wire logic [33 : 0]	input
alu_adder_result_ex_o	var logic [31 : 0]	output	Outputs to LSU
result_ex_o	var logic [31 : 0]	output
branch_target_o	var logic [31 : 0]	output	to IF
branch_decision_o	var logic	output	to ID
ex_valid_o	var logic	output	EX has valid output

Instances

• ibex_top : ibex_top

  • u_ibex_core : ibex_core

    • ex_block_i : ibex_ex_block

Submodules

• ibex_ex_block

  • alu_i : ibex_alu

  • g_no_branch_target_alu : [if !(BranchTargetALU)]

  • gen_multdiv_fast : []

    • multdiv_i : ibex_multdiv_fast

  • gen_multdiv_m : []

  • gen_multdiv_sva_idle_fast : []

Flow Diagram of ibex_ex_block

Sub-Instances Diagram of ibex_ex_block

Schematic Diagram of ibex_ex_block

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