Module ibex_cs_registers

ibex_cs_registers #( .DbgTriggerEn(DbgTriggerEn), .DbgHwBreakNum(DbgHwBreakNum), .DataIndTiming(DataIndTiming), .DummyInstructions(DummyInstructions), .ShadowCSR(ShadowCSR), .ICache(ICache), .MHPMCounterNum(MHPMCounterNum), .MHPMCounterWidth(MHPMCounterWidth), .PMPEnable(PMPEnable), .PMPGranularity(PMPGranularity), .PMPNumRegions(PMPNumRegions), .PMPRstCfg(PMPRstCfg), .PMPRstAddr(PMPRstAddr), .PMPRstMsecCfg(PMPRstMsecCfg), .RV32E(RV32E), .RV32M(RV32M), .RV32B(RV32B) ) u_ibex_cs_registers ( .clk_i(clk_i), .rst_ni(rst_ni), .hart_id_i(hart_id_i), .priv_mode_id_o(priv_mode_id_o), .priv_mode_lsu_o(priv_mode_lsu_o), .csr_mstatus_tw_o(csr_mstatus_tw_o), .csr_mtvec_o(csr_mtvec_o), .csr_mtvec_init_i(csr_mtvec_init_i), .boot_addr_i(boot_addr_i), .csr_access_i(csr_access_i), .csr_addr_i(csr_addr_i), .csr_wdata_i(csr_wdata_i), .csr_op_i(csr_op_i), .csr_op_en_i(csr_op_en_i), .csr_rdata_o(csr_rdata_o), .irq_software_i(irq_software_i), .irq_timer_i(irq_timer_i), .irq_external_i(irq_external_i), .irq_fast_i(irq_fast_i), .nmi_mode_i(nmi_mode_i), .irq_pending_o(irq_pending_o), .irqs_o(irqs_o), .csr_mstatus_mie_o(csr_mstatus_mie_o), .csr_mepc_o(csr_mepc_o), .csr_mtval_o(csr_mtval_o), .csr_pmp_cfg_o(csr_pmp_cfg_o), .csr_pmp_addr_o(csr_pmp_addr_o), .csr_pmp_mseccfg_o(csr_pmp_mseccfg_o), .debug_mode_i(debug_mode_i), .debug_mode_entering_i(debug_mode_entering_i), .debug_cause_i(debug_cause_i), .debug_csr_save_i(debug_csr_save_i), .csr_depc_o(csr_depc_o), .debug_single_step_o(debug_single_step_o), .debug_ebreakm_o(debug_ebreakm_o), .debug_ebreaku_o(debug_ebreaku_o), .trigger_match_o(trigger_match_o), .pc_if_i(pc_if_i), .pc_id_i(pc_id_i), .pc_wb_i(pc_wb_i), .data_ind_timing_o(data_ind_timing_o), .dummy_instr_en_o(dummy_instr_en_o), .dummy_instr_mask_o(dummy_instr_mask_o), .dummy_instr_seed_en_o(dummy_instr_seed_en_o), .dummy_instr_seed_o(dummy_instr_seed_o), .icache_enable_o(icache_enable_o), .csr_shadow_err_o(csr_shadow_err_o), .ic_scr_key_valid_i(ic_scr_key_valid_i), .csr_save_if_i(csr_save_if_i), .csr_save_id_i(csr_save_id_i), .csr_save_wb_i(csr_save_wb_i), .csr_restore_mret_i(csr_restore_mret_i), .csr_restore_dret_i(csr_restore_dret_i), .csr_save_cause_i(csr_save_cause_i), .csr_mcause_i(csr_mcause_i), .csr_mtval_i(csr_mtval_i), .illegal_csr_insn_o(illegal_csr_insn_o), .double_fault_seen_o(double_fault_seen_o), .instr_ret_i(instr_ret_i), .instr_ret_compressed_i(instr_ret_compressed_i), .instr_ret_spec_i(instr_ret_spec_i), .instr_ret_compressed_spec_i(instr_ret_compressed_spec_i), .iside_wait_i(iside_wait_i), .jump_i(jump_i), .branch_i(branch_i), .branch_taken_i(branch_taken_i), .mem_load_i(mem_load_i), .mem_store_i(mem_store_i), .dside_wait_i(dside_wait_i), .mul_wait_i(mul_wait_i), .div_wait_i(div_wait_i) );

Block Diagram of ibex_cs_registers

Parameters

Name	Default	Description
DbgTriggerEn	0
DbgHwBreakNum	1
DataIndTiming	1'b0
DummyInstructions	1'b0
ShadowCSR	1'b0
ICache	1'b0
MHPMCounterNum	10
MHPMCounterWidth	40
PMPEnable	0
PMPGranularity	0
PMPNumRegions	4
PMPRstCfg	ibex_pkg::PmpCfgRst
PMPRstAddr	ibex_pkg::PmpAddrRst
PMPRstMsecCfg	ibex_pkg::PmpMseccfgRst
RV32E	0
RV32M	ibex_pkg::RV32MFast
RV32B	ibex_pkg::RV32BNone

Ports

Name	Type	Direction	Description
clk_i	wire logic	input	Clock and Reset
rst_ni	wire logic	input
hart_id_i	wire logic [31 : 0]	input	Hart ID
priv_mode_id_o	var ibex_pkg::priv_lvl_e	output	Privilege mode
priv_mode_lsu_o	var ibex_pkg::priv_lvl_e	output
csr_mstatus_tw_o	var logic	output
csr_mtvec_o	var logic [31 : 0]	output	mtvec
csr_mtvec_init_i	wire logic	input
boot_addr_i	wire logic [31 : 0]	input
csr_access_i	wire logic	input	Interface to registers (SRAM like)
csr_addr_i	wire ibex_pkg::csr_num_e	input
csr_wdata_i	wire logic [31 : 0]	input
csr_op_i	wire ibex_pkg::csr_op_e	input
csr_op_en_i	wire logic	input
csr_rdata_o	var logic [31 : 0]	output
irq_software_i	wire logic	input	interrupts
irq_timer_i	wire logic	input
irq_external_i	wire logic	input
irq_fast_i	wire logic [14 : 0]	input
nmi_mode_i	wire logic	input
irq_pending_o	var logic	output	interrupt request pending
irqs_o	var ibex_pkg::irqs_t	output	interrupt requests qualified with mie
csr_mstatus_mie_o	var logic	output
csr_mepc_o	var logic [31 : 0]	output
csr_mtval_o	var logic [31 : 0]	output
csr_pmp_cfg_o	var pmp_cfg_t	output	PMP
csr_pmp_addr_o	var logic [33 : 0]	output
csr_pmp_mseccfg_o	var ibex_pkg::pmp_mseccfg_t	output
debug_mode_i	wire logic	input	debug
debug_mode_entering_i	wire logic	input
debug_cause_i	wire ibex_pkg::dbg_cause_e	input
debug_csr_save_i	wire logic	input
csr_depc_o	var logic [31 : 0]	output
debug_single_step_o	var logic	output
debug_ebreakm_o	var logic	output
debug_ebreaku_o	var logic	output
trigger_match_o	var logic	output
pc_if_i	wire logic [31 : 0]	input
pc_id_i	wire logic [31 : 0]	input
pc_wb_i	wire logic [31 : 0]	input
data_ind_timing_o	var logic	output	CPU control and status bits
dummy_instr_en_o	var logic	output
dummy_instr_mask_o	var logic [2 : 0]	output
dummy_instr_seed_en_o	var logic	output
dummy_instr_seed_o	var logic [31 : 0]	output
icache_enable_o	var logic	output
csr_shadow_err_o	var logic	output
ic_scr_key_valid_i	wire logic	input
csr_save_if_i	wire logic	input	Exception save/restore
csr_save_id_i	wire logic	input
csr_save_wb_i	wire logic	input
csr_restore_mret_i	wire logic	input
csr_restore_dret_i	wire logic	input
csr_save_cause_i	wire logic	input
csr_mcause_i	wire ibex_pkg::exc_cause_t	input
csr_mtval_i	wire logic [31 : 0]	input
illegal_csr_insn_o	var logic	output	access to non-existent CSR,
double_fault_seen_o	var logic	output	with wrong priviledge level, or missing write permissions
instr_ret_i	wire logic	input	Performance Counters instr retired in ID/EX stage
instr_ret_compressed_i	wire logic	input	compressed instr retired
instr_ret_spec_i	wire logic	input	speculative instr_ret_i
instr_ret_compressed_spec_i	wire logic	input	speculative instr_ret_compressed_i
iside_wait_i	wire logic	input	core waiting for the iside
jump_i	wire logic	input	jump instr seen (j, jr, jal, jalr)
branch_i	wire logic	input	branch instr seen (bf, bnf)
branch_taken_i	wire logic	input	branch was taken
mem_load_i	wire logic	input	load from memory in this cycle
mem_store_i	wire logic	input	store to memory in this cycle
dside_wait_i	wire logic	input	core waiting for the dside
mul_wait_i	wire logic	input	core waiting for multiply
div_wait_i	wire logic	input	core waiting for divide

Assertions

Name	Kind	Description
ibex_cs_registers.PMPAddrRstLowBitsZero_A	immediate assert	(PMPRstAddr[i][33 - PMPAddrWidth : 0] == '0)
ibex_cs_registers.IbexCsrOpEnRequiresAccess	concurent assert	////////////// Assertions // ////////////// disable iff((!rst_ni)!=='0)(csr_op_en_i |-> csr_access_i)

Structs

typedef struct status_t

typedef struct status_stk_t

typedef struct dcsr_t

typedef struct cpu_ctrl_sts_part_t

Partial CPU control and status register fields ICache scramble key valid (ic_scr_key_valid) is registered seperately to this struct. This is because it is sampled from the top-level every cycle whilst the other fields only change occasionally.

Always Blocks

always_comb @()

read logic

always_comb @()

write logic

always_ff @(posedge clk_i or negedge rst_ni)

Update current priv level

always_comb @()

CSR operation logic

mcountinhibit_update :

always_comb @()

update enable signals

gen_mhpmcounter_incr :

always_comb @()

event selection (hardwired) & control

gen_mhpmevent :

always_comb @()

event selector (hardwired, 0 means no event)

Functions

function logic

is_mml_m_exec_cfg(ibex_pkg::pmp_cfg_t pmp_cfg)

Is a PMP config a locked one that allows M-mode execution when MSECCFG.MML is set (either M mode alone or shared M/U mode execution)?

Parameters:

pmp_cfg (ibex_pkg::pmp_cfg_t)

Instances

• ibex_top : ibex_top

  • u_ibex_core : ibex_core

    • cs_registers_i : ibex_cs_registers

Submodules

• ibex_cs_registers

  • g_mcountinhibit_reduced : []

  • g_no_pmp_tieoffs : [if !(PMPEnable)]

  • gen_cntrs : [for (genvar i=0;i<29;i++)]

  • gen_no_dit : [if !(DataIndTiming)]

  • gen_no_dummy : [if !(DummyInstructions)]

  • gen_no_icache : [if !(ICache)]

  • gen_no_trigger_regs : [if !(DbgTriggerEn)]

  • mcycle_counter_i : ibex_counter

  • minstret_counter_i : ibex_counter

  • u_cpuctrlsts_part_csr : ibex_csr

  • u_dcsr_csr : ibex_csr

  • u_depc_csr : ibex_csr

  • u_dscratch0_csr : ibex_csr

  • u_dscratch1_csr : ibex_csr

  • u_mcause_csr : ibex_csr

  • u_mepc_csr : ibex_csr

  • u_mie_csr : ibex_csr

  • u_mscratch_csr : ibex_csr

  • u_mstack_cause_csr : ibex_csr

  • u_mstack_csr : ibex_csr

  • u_mstack_epc_csr : ibex_csr

  • u_mstatus_csr : ibex_csr

  • u_mtval_csr : ibex_csr

  • u_mtvec_csr : ibex_csr

Flow Diagram of ibex_cs_registers

Sub-Instances Diagram of ibex_cs_registers

Schematic Diagram of ibex_cs_registers

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