Module ibex_top_tracing

ibex_top_tracing #( .PMPEnable(PMPEnable), .PMPGranularity(PMPGranularity), .PMPNumRegions(PMPNumRegions), .MHPMCounterNum(MHPMCounterNum), .MHPMCounterWidth(MHPMCounterWidth), .RV32E(RV32E), .RV32M(RV32M), .RV32B(RV32B), .RegFile(RegFile), .BranchTargetALU(BranchTargetALU), .WritebackStage(WritebackStage), .ICache(ICache), .ICacheECC(ICacheECC), .BranchPredictor(BranchPredictor), .DbgTriggerEn(DbgTriggerEn), .DbgHwBreakNum(DbgHwBreakNum), .SecureIbex(SecureIbex), .ICacheScramble(ICacheScramble), .RndCnstLfsrSeed(RndCnstLfsrSeed), .RndCnstLfsrPerm(RndCnstLfsrPerm), .DmBaseAddr(DmBaseAddr), .DmAddrMask(DmAddrMask), .DmHaltAddr(DmHaltAddr), .DmExceptionAddr(DmExceptionAddr) ) u_ibex_top_tracing ( .clk_i(clk_i), .rst_ni(rst_ni), .test_en_i(test_en_i), .scan_rst_ni(scan_rst_ni), .ram_cfg_i(ram_cfg_i), .hart_id_i(hart_id_i), .boot_addr_i(boot_addr_i), .instr_req_o(instr_req_o), .instr_gnt_i(instr_gnt_i), .instr_rvalid_i(instr_rvalid_i), .instr_addr_o(instr_addr_o), .instr_rdata_i(instr_rdata_i), .instr_rdata_intg_i(instr_rdata_intg_i), .instr_err_i(instr_err_i), .data_req_o(data_req_o), .data_gnt_i(data_gnt_i), .data_rvalid_i(data_rvalid_i), .data_we_o(data_we_o), .data_be_o(data_be_o), .data_addr_o(data_addr_o), .data_wdata_o(data_wdata_o), .data_wdata_intg_o(data_wdata_intg_o), .data_rdata_i(data_rdata_i), .data_rdata_intg_i(data_rdata_intg_i), .data_err_i(data_err_i), .irq_software_i(irq_software_i), .irq_timer_i(irq_timer_i), .irq_external_i(irq_external_i), .irq_fast_i(irq_fast_i), .irq_nm_i(irq_nm_i), .scramble_key_valid_i(scramble_key_valid_i), .scramble_key_i(scramble_key_i), .scramble_nonce_i(scramble_nonce_i), .scramble_req_o(scramble_req_o), .debug_req_i(debug_req_i), .crash_dump_o(crash_dump_o), .double_fault_seen_o(double_fault_seen_o), .fetch_enable_i(fetch_enable_i), .alert_minor_o(alert_minor_o), .alert_major_internal_o(alert_major_internal_o), .alert_major_bus_o(alert_major_bus_o), .core_sleep_o(core_sleep_o) );

Block Diagram of ibex_top_tracing

Top level module of the ibex RISC-V core with tracing enabled

Parameters

Name	Default	Description
PMPEnable	1'b0
PMPGranularity	0
PMPNumRegions	4
MHPMCounterNum	0
MHPMCounterWidth	40
RV32E	1'b0
RV32M	RV32MFast
RV32B	RV32BNone
RegFile	RegFileFF
BranchTargetALU	1'b0
WritebackStage	1'b0
ICache	1'b0
ICacheECC	1'b0
BranchPredictor	1'b0
DbgTriggerEn	1'b0
DbgHwBreakNum	1
SecureIbex	1'b0
ICacheScramble	1'b0
RndCnstLfsrSeed	RndCnstLfsrSeedDefault
RndCnstLfsrPerm	RndCnstLfsrPermDefault
DmBaseAddr	32'h1A110000
DmAddrMask	32'h00000FFF
DmHaltAddr	32'h1A110800
DmExceptionAddr	32'h1A110808

Ports

Name	Type	Direction	Description
clk_i	wire logic	input	Clock and Reset
rst_ni	wire logic	input
test_en_i	wire logic	input	enable all clock gates for testing
scan_rst_ni	wire logic	input
ram_cfg_i	wire prim_ram_1p_pkg::ram_1p_cfg_t	input
hart_id_i	wire logic [31 : 0]	input
boot_addr_i	wire logic [31 : 0]	input
instr_req_o	var logic	output	Instruction memory interface
instr_gnt_i	wire logic	input
instr_rvalid_i	wire logic	input
instr_addr_o	var logic [31 : 0]	output
instr_rdata_i	wire logic [31 : 0]	input
instr_rdata_intg_i	wire logic [6 : 0]	input
instr_err_i	wire logic	input
data_req_o	var logic	output	Data memory interface
data_gnt_i	wire logic	input
data_rvalid_i	wire logic	input
data_we_o	var logic	output
data_be_o	var logic [3 : 0]	output
data_addr_o	var logic [31 : 0]	output
data_wdata_o	var logic [31 : 0]	output
data_wdata_intg_o	var logic [6 : 0]	output
data_rdata_i	wire logic [31 : 0]	input
data_rdata_intg_i	wire logic [6 : 0]	input
data_err_i	wire logic	input
irq_software_i	wire logic	input	Interrupt inputs
irq_timer_i	wire logic	input
irq_external_i	wire logic	input
irq_fast_i	wire logic [14 : 0]	input
irq_nm_i	wire logic	input	non-maskeable interrupt
scramble_key_valid_i	wire logic	input	Scrambling Interface
scramble_key_i	wire logic [SCRAMBLE_KEY_W - 1 : 0]	input
scramble_nonce_i	wire logic [SCRAMBLE_NONCE_W - 1 : 0]	input
scramble_req_o	var logic	output
debug_req_i	wire logic	input	Debug Interface
crash_dump_o	var crash_dump_t	output
double_fault_seen_o	var logic	output
fetch_enable_i	wire ibex_mubi_t	input	CPU Control Signals
alert_minor_o	var logic	output
alert_major_internal_o	var logic	output
alert_major_bus_o	var logic	output
core_sleep_o	var logic	output

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