Module prim_secded_inv_72_64_enc

prim_secded_inv_72_64_enc u_prim_secded_inv_72_64_enc ( .data_i(data_i), .data_o(data_o) );

Block Diagram of prim_secded_inv_72_64_enc

SECDED encoder generated by util/design/secded_gen.py

Ports

Name	Type	Direction	Description
data_i	wire logic [63 : 0]	input
data_o	var logic [71 : 0]	output

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