[source]

Module ibex_prefetch_buffer

ResetAllclk_ilogicrst_nilogicreq_ilogicbranch_ilogicaddr_i[31:0]logicready_ilogicinstr_gnt_ilogicinstr_rdata_i[31:0]logicinstr_err_ilogicinstr_rvalid_ilogicvalid_ologicrdata_ologic[31:0]addr_ologic[31:0]err_ologicerr_plus2_ologicinstr_req_ologicinstr_addr_ologic[31:0]busy_ologic

Block Diagram of ibex_prefetch_buffer

Prefetcher Buffer for 32 bit memory interface

Prefetch Buffer that caches instructions. This cuts overly long critical paths to the instruction cache.

Parameters

Name

Default

Description
ResetAll

1'b0
Ports

Name

Type

Direction

Description
clk_i

wire logic

input
rst_ni

wire logic

input
req_i

wire logic

input
branch_i

wire logic

input
addr_i

wire logic [31 : 0]

input
ready_i

wire logic

input
valid_o

var logic

output
rdata_o

var logic [31 : 0]

output
addr_o

var logic [31 : 0]

output
err_o

var logic

output
err_plus2_o

var logic

output
instr_req_o

var logic

output

goes to instruction memory / instruction cache
instr_gnt_i

wire logic

input
instr_addr_o

var logic [31 : 0]

output
instr_rdata_i

wire logic [31 : 0]

input
instr_err_i

wire logic

input
instr_rvalid_i

wire logic

input
busy_o

var logic

output

Prefetch Buffer Status

Always Blocks

always_ff @(posedge clk_i or negedge rst_ni)

///////////// Registers // /////////////

Instances

Submodules

  • ibex_prefetch_buffer

    • fifo_i : ibex_fetch_fifo

    • g_fetch_addr_nr : [if !(ResetAll)]

    • g_outstanding_reqs : [for (genvar i=0;i<NUM_REQS;i++)]

    • g_stored_addr_nr : [if !(ResetAll)]

    • gen_rd_rev : [for (genvar i=0;i<NUM_REQS;i++)]

fifo_i (ibex_fetch_fifo) g_fetch_addr_nr g_stored_addr_nr prefetch_buffer_i (ibex_prefetch_buffer)

Flow Diagram of ibex_prefetch_buffer

fifo_i (ibex_fetch_fifo) clk_i rst_ni in_rdata_i in_err_i out_valid_o out_ready_i out_addr_o out_rdata_o out_err_o out_err_plus2_o g_fetch_addr_nr g_req0 g_reqtop g_outstanding_reqs g_stored_addr_nr gen_rd_rev prefetch_buffer_i (ibex_prefetch_buffer) clk_i rst_ni ready_i valid_o rdata_o addr_o err_o err_plus2_o instr_rdata_i instr_err_i

Sub-Instances Diagram of ibex_prefetch_buffer

fifo_i (ibex_fetch_fifo) clk_i rst_ni clear_i busy_o in_valid_i in_addr_i in_rdata_i in_err_i out_valid_o out_ready_i out_addr_o out_rdata_o out_err_o out_err_plus2_o busy_o rdata_outstanding_q instr_req_o fifo_clear branch_i fifo_ready fifo_busy rdata_outstanding_rev valid_new_req req_i fifo_ready branch_i rdata_outstanding_q valid_req valid_req_q valid_new_req valid_req_d valid_req instr_gnt_i discard_req_d valid_req_q branch_i discard_req_q stored_addr_en valid_new_req valid_req_q instr_gnt_i stored_addr_d instr_addr fetch_addr_en branch_i valid_new_req valid_req_q fetch_addr_d branch_i fetch_addr_q addr_i valid_new_req valid_req_q instr_addr stored_addr_q valid_req_q addr_i branch_i fetch_addr_q instr_addr_w_aligned instr_addr rdata_outstanding_s rdata_outstanding_n instr_rvalid_i branch_discard_s branch_discard_n instr_rvalid_i fifo_valid instr_rvalid_i branch_discard_q fifo_addr addr_i instr_req_o valid_req instr_addr_o instr_addr_w_aligned valid_req_q rst_ni clk_i valid_req_d discard_req_q discard_req_d rdata_outstanding_q rdata_outstanding_s branch_discard_q branch_discard_s fetch_addr_q fetch_addr_d clk_i fetch_addr_en g_fetch_addr_nr rdata_outstanding_n valid_req instr_gnt_i rdata_outstanding_q branch_discard_n valid_req instr_gnt_i discard_req_d branch_i rdata_outstanding_q branch_discard_q g_req0 rdata_outstanding_n valid_req instr_gnt_i rdata_outstanding_q branch_discard_n valid_req instr_gnt_i discard_req_d rdata_outstanding_q branch_i branch_discard_q g_reqtop g_outstanding_reqs stored_addr_q stored_addr_d clk_i stored_addr_en g_stored_addr_nr rdata_outstanding_rev rdata_outstanding_q gen_rd_rev prefetch_buffer_i (ibex_prefetch_buffer) clk_i rst_ni req_i branch_i addr_i ready_i valid_o rdata_o addr_o err_o err_plus2_o instr_req_o instr_gnt_i instr_addr_o instr_rdata_i instr_err_i instr_rvalid_i busy_o

Schematic Diagram of ibex_prefetch_buffer