[source]

Module ibex_top

PMPEnablePMPGranularityPMPNumRegionsMHPMCounterNumMHPMCounterWidthPMPRstCfgPMPRstAddrPMPRstMsecCfgRV32ERV32MRV32BRegFileBranchTargetALUWritebackStageICacheICacheECCBranchPredictorDbgTriggerEnDbgHwBreakNumSecureIbexICacheScrambleICacheScrNumPrinceRoundsHalfRndCnstLfsrSeedRndCnstLfsrPermDmBaseAddrDmAddrMaskDmHaltAddrDmExceptionAddrRndCnstIbexKeyRndCnstIbexNonceclk_ilogicrst_nilogictest_en_ilogicram_cfg_iprim_ram_1p_pkg::ram_1p_cfg_thart_id_i[31:0]logicboot_addr_i[31:0]logicinstr_gnt_ilogicinstr_rvalid_ilogicinstr_rdata_i[31:0]logicinstr_rdata_intg_i[6:0]logicinstr_err_ilogicdata_gnt_ilogicdata_rvalid_ilogicdata_rdata_i[31:0]logicdata_rdata_intg_i[6:0]logicdata_err_ilogicirq_software_ilogicirq_timer_ilogicirq_external_ilogicirq_fast_i[14:0]logicirq_nm_ilogicscramble_key_valid_ilogicscramble_key_i[SCRAMBLE_KEY_W-1:0]logicscramble_nonce_i[SCRAMBLE_NONCE_W-1:0]logicdebug_req_ilogicfetch_enable_iibex_mubi_tscan_rst_nilogicinstr_req_ologicinstr_addr_ologic[31:0]data_req_ologicdata_we_ologicdata_be_ologic[3:0]data_addr_ologic[31:0]data_wdata_ologic[31:0]data_wdata_intg_ologic[6:0]scramble_req_ologiccrash_dump_ocrash_dump_tdouble_fault_seen_ologicrvfi_validlogicrvfi_orderlogic[63:0]rvfi_insnlogic[31:0]rvfi_traplogicrvfi_haltlogicrvfi_intrlogicrvfi_modelogic[1:0]rvfi_ixllogic[1:0]rvfi_rs1_addrlogic[4:0]rvfi_rs2_addrlogic[4:0]rvfi_rs3_addrlogic[4:0]rvfi_rs1_rdatalogic[31:0]rvfi_rs2_rdatalogic[31:0]rvfi_rs3_rdatalogic[31:0]rvfi_rd_addrlogic[4:0]rvfi_rd_wdatalogic[31:0]rvfi_pc_rdatalogic[31:0]rvfi_pc_wdatalogic[31:0]rvfi_mem_addrlogic[31:0]rvfi_mem_rmasklogic[3:0]rvfi_mem_wmasklogic[3:0]rvfi_mem_rdatalogic[31:0]rvfi_mem_wdatalogic[31:0]rvfi_ext_pre_miplogic[31:0]rvfi_ext_post_miplogic[31:0]rvfi_ext_nmilogicrvfi_ext_nmi_intlogicrvfi_ext_debug_reqlogicrvfi_ext_debug_modelogicrvfi_ext_rf_wr_suppresslogicrvfi_ext_mcyclelogic[63:0]rvfi_ext_mhpmcounterslogic[31:0]rvfi_ext_mhpmcountershlogic[31:0]rvfi_ext_ic_scr_key_validlogicrvfi_ext_irq_validlogicalert_minor_ologicalert_major_internal_ologicalert_major_bus_ologiccore_sleep_ologic

Block Diagram of ibex_top

Top level module of the ibex RISC-V core

Parameters

Name

Default

Description
PMPEnable

1'b0
PMPGranularity

0
PMPNumRegions

4
MHPMCounterNum

0
MHPMCounterWidth

40
PMPRstCfg

ibex_pkg::PmpCfgRst
PMPRstAddr

ibex_pkg::PmpAddrRst
PMPRstMsecCfg

ibex_pkg::PmpMseccfgRst
RV32E

1'b0
RV32M

RV32MFast
RV32B

RV32BNone
RegFile

RegFileFF
BranchTargetALU

1'b0
WritebackStage

1'b0
ICache

1'b0
ICacheECC

1'b0
BranchPredictor

1'b0
DbgTriggerEn

1'b0
DbgHwBreakNum

1
SecureIbex

1'b0
ICacheScramble

1'b0
ICacheScrNumPrinceRoundsHalf

2
RndCnstLfsrSeed

RndCnstLfsrSeedDefault
RndCnstLfsrPerm

RndCnstLfsrPermDefault
DmBaseAddr

32'h1A110000
DmAddrMask

32'h00000FFF
DmHaltAddr

32'h1A110800
DmExceptionAddr

32'h1A110808
RndCnstIbexKey

RndCnstIbexKeyDefault

Default seed and nonce for scrambling
RndCnstIbexNonce

RndCnstIbexNonceDefault
Ports

Name

Type

Direction

Description
clk_i

wire logic

input

Clock and Reset
rst_ni

wire logic

input
test_en_i

wire logic

input

enable all clock gates for testing
ram_cfg_i

wire prim_ram_1p_pkg::ram_1p_cfg_t

input
hart_id_i

wire logic [31 : 0]

input
boot_addr_i

wire logic [31 : 0]

input
instr_req_o

var logic

output

Instruction memory interface
instr_gnt_i

wire logic

input
instr_rvalid_i

wire logic

input
instr_addr_o

var logic [31 : 0]

output
instr_rdata_i

wire logic [31 : 0]

input
instr_rdata_intg_i

wire logic [6 : 0]

input
instr_err_i

wire logic

input
data_req_o

var logic

output

Data memory interface
data_gnt_i

wire logic

input
data_rvalid_i

wire logic

input
data_we_o

var logic

output
data_be_o

var logic [3 : 0]

output
data_addr_o

var logic [31 : 0]

output
data_wdata_o

var logic [31 : 0]

output
data_wdata_intg_o

var logic [6 : 0]

output
data_rdata_i

wire logic [31 : 0]

input
data_rdata_intg_i

wire logic [6 : 0]

input
data_err_i

wire logic

input
irq_software_i

wire logic

input

Interrupt inputs
irq_timer_i

wire logic

input
irq_external_i

wire logic

input
irq_fast_i

wire logic [14 : 0]

input
irq_nm_i

wire logic

input

non-maskeable interrupt
scramble_key_valid_i

wire logic

input

Scrambling Interface
scramble_key_i

wire logic [SCRAMBLE_KEY_W - 1 : 0]

input
scramble_nonce_i

wire logic [SCRAMBLE_NONCE_W - 1 : 0]

input
scramble_req_o

var logic

output
debug_req_i

wire logic

input

Debug Interface
crash_dump_o

var crash_dump_t

output
double_fault_seen_o

var logic

output
rvfi_valid

var logic

output
rvfi_order

var logic [63 : 0]

output
rvfi_insn

var logic [31 : 0]

output
rvfi_trap

var logic

output
rvfi_halt

var logic

output
rvfi_intr

var logic

output
rvfi_mode

var logic [1 : 0]

output
rvfi_ixl

var logic [1 : 0]

output
rvfi_rs1_addr

var logic [4 : 0]

output
rvfi_rs2_addr

var logic [4 : 0]

output
rvfi_rs3_addr

var logic [4 : 0]

output
rvfi_rs1_rdata

var logic [31 : 0]

output
rvfi_rs2_rdata

var logic [31 : 0]

output
rvfi_rs3_rdata

var logic [31 : 0]

output
rvfi_rd_addr

var logic [4 : 0]

output
rvfi_rd_wdata

var logic [31 : 0]

output
rvfi_pc_rdata

var logic [31 : 0]

output
rvfi_pc_wdata

var logic [31 : 0]

output
rvfi_mem_addr

var logic [31 : 0]

output
rvfi_mem_rmask

var logic [3 : 0]

output
rvfi_mem_wmask

var logic [3 : 0]

output
rvfi_mem_rdata

var logic [31 : 0]

output
rvfi_mem_wdata

var logic [31 : 0]

output
rvfi_ext_pre_mip

var logic [31 : 0]

output
rvfi_ext_post_mip

var logic [31 : 0]

output
rvfi_ext_nmi

var logic

output
rvfi_ext_nmi_int

var logic

output
rvfi_ext_debug_req

var logic

output
rvfi_ext_debug_mode

var logic

output
rvfi_ext_rf_wr_suppress

var logic

output
rvfi_ext_mcycle

var logic [63 : 0]

output
rvfi_ext_mhpmcounters

var logic [31 : 0]

output
rvfi_ext_mhpmcountersh

var logic [31 : 0]

output
rvfi_ext_ic_scr_key_valid

var logic

output
rvfi_ext_irq_valid

var logic

output
fetch_enable_i

wire ibex_mubi_t

input

CPU Control Signals
alert_minor_o

var logic

output
alert_major_internal_o

var logic

output
alert_major_bus_o

var logic

output
core_sleep_o

var logic

output
scan_rst_ni

wire logic

input

DFT bypass controls
Assertions

Name

Kind

Description

ibex_top.ScrambleKeyAppliedAtTagBank_A

concurent assert

Ensure that when a scramble key is received, it is correctly applied to the icache scrambled memory primitives. The upper bound in the cycle ranges below is not exact, but it should not take more than 10 cycles.

disable iff((!rst_ni)!=='0)(scramble_key_valid_i |-> (## [0 : 10] (tag_bank.key_valid_i && (tag_bank.key_i == sampled_scramble_key))))

ibex_top.ScrambleKeyAppliedAtDataBank_A

concurent assert

 
disable iff((!rst_ni)!=='0)(scramble_key_valid_i |-> (## [0 : 10] (data_bank.key_valid_i && (data_bank.key_i == sampled_scramble_key))))

ibex_top.DmHaltAddrInRange_A

immediate assert

Parameter assertions

((DmHaltAddr & ~ DmAddrMask) == DmBaseAddr)

ibex_top.DmExceptionAddrInRange_A

immediate assert

 
((DmExceptionAddr & ~ DmAddrMask) == DmBaseAddr)

ibex_top.IbexInstrReqX

concurent assert

X checks for top-level outputs

disable iff((!rst_ni)!=='0)! $isunknown(instr_req_o)

ibex_top.IbexInstrReqPayloadXKnownEnable

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(instr_req_o)

ibex_top.IbexInstrReqPayloadX

concurent assert

 
disable iff((!rst_ni)!=='0)(instr_req_o |-> ! $isunknown(instr_addr_o))

ibex_top.IbexDataReqX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(data_req_o)

ibex_top.IbexDataReqPayloadXKnownEnable

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(data_req_o)

ibex_top.IbexDataReqPayloadX

concurent assert

 
disable iff((!rst_ni)!=='0)(data_req_o |-> ! $isunknown({data_we_o, data_be_o, data_addr_o, data_wdata_o, data_wdata_intg_o}))

ibex_top.IbexScrambleReqX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(scramble_req_o)

ibex_top.IbexDoubleFaultSeenX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(double_fault_seen_o)

ibex_top.IbexAlertMinorX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(alert_minor_o)

ibex_top.IbexAlertMajorInternalX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(alert_major_internal_o)

ibex_top.IbexAlertMajorBusX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(alert_major_bus_o)

ibex_top.IbexCoreSleepX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(core_sleep_o)

ibex_top.IbexTestEnX

concurent assert

X check for top-level inputs

disable iff((!rst_ni)!=='0)! $isunknown(test_en_i)

ibex_top.IbexRamCfgX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(ram_cfg_i)

ibex_top.IbexHartIdX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(hart_id_i)

ibex_top.IbexBootAddrX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(boot_addr_i)

ibex_top.IbexInstrGntX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(instr_gnt_i)

ibex_top.IbexInstrRValidX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(instr_rvalid_i)

ibex_top.IbexInstrRPayloadXKnownEnable

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(instr_rvalid_i)

ibex_top.IbexInstrRPayloadX

concurent assert

 
disable iff((!rst_ni)!=='0)(instr_rvalid_i |-> ! $isunknown({instr_rdata_i, instr_rdata_intg_i, instr_err_i}))

ibex_top.IbexDataGntX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(data_gnt_i)

ibex_top.IbexDataRValidX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(data_rvalid_i)

ibex_top.MaxOutstandingDSideAccessesCorrect

concurent assert

We should never start a new data request if we've already got the maximum outstanding. We can start a new request in the same cycle an old one ends, in which case we'll see all pending accesses valid but one will be ending this cycle so the empty slot can be immediately used by the new request.

disable iff((!rst_ni)!=='0)(data_req_o |-> (~ pending_dside_accesses_q[MaxOutstandingDSideAccesses - 1].valid | data_rvalid_i))

ibex_top.PendingAccessTrackingCorrect

concurent assert

Should only see a request response if we're expecting one

disable iff((!rst_ni)!=='0)(data_rvalid_i |-> pending_dside_accesses_q[0])

ibex_top.IbexDataRPayloadXKnownEnable

concurent assert

For SecureIbex responses to both writes and reads must specify rdata and rdata_intg (for writes rdata is effectively ignored by rdata_intg still checked against rdata)

disable iff((!rst_ni)!=='0)! $isunknown(data_rvalid_i)

ibex_top.IbexDataRPayloadX

concurent assert

 
disable iff((!rst_ni)!=='0)(data_rvalid_i |-> ! $isunknown({data_rdata_i, data_rdata_intg_i}))

ibex_top.IbexDataRPayloadXKnownEnable

concurent assert

Without SecureIbex data_rdata_i and data_rdata_intg_i are only relevant to reads. Check neither are X on a response to a read.

disable iff((!rst_ni)!=='0)! $isunknown((data_rvalid_i & pending_dside_accesses_q[0].is_read))

ibex_top.IbexDataRPayloadX

concurent assert

 
disable iff((!rst_ni)!=='0)((data_rvalid_i & pending_dside_accesses_q[0].is_read) |-> ! $isunknown({data_rdata_i, data_rdata_intg_i}))

ibex_top.IbexDataRErrPayloadXKnownEnable

concurent assert

data_err_i relevant to both reads and writes. Check it isn't X on any response.

disable iff((!rst_ni)!=='0)! $isunknown(data_rvalid_i)

ibex_top.IbexDataRErrPayloadX

concurent assert

 
disable iff((!rst_ni)!=='0)(data_rvalid_i |-> ! $isunknown(data_err_i))

ibex_top.DoubleFaultSinglePulse

concurent assert

We should only have a single assertion of double_fault_seen in the delay buffer

disable iff((!rst_ni)!=='0)$onehot0(double_fault_seen_delay_buffer)

ibex_top.DoubleFaultPulseSeenOnDoubleFault

concurent assert

If we predict a double_fault_seen_o we should see one in the delay buffer

disable iff((!rst_ni)!=='0)(double_fault_seen_predicted |-> | double_fault_seen_delay_buffer)

ibex_top.DoubleFaultPulseOnlyOnDoubleFault

concurent assert

If double_fault_seen_o is asserted we should see predict one occurring within a bounded time

disable iff((!rst_ni)!=='0)(double_fault_seen_o |-> (## [0 : DoubleFaultSeenLatency] double_fault_seen_predicted))

ibex_top.IbexIrqX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown({irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i})

ibex_top.IbexScrambleKeyValidX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(scramble_key_valid_i)

ibex_top.IbexScramblePayloadXKnownEnable

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(scramble_key_valid_i)

ibex_top.IbexScramblePayloadX

concurent assert

 
disable iff((!rst_ni)!=='0)(scramble_key_valid_i |-> ! $isunknown({scramble_key_i, scramble_nonce_i}))

ibex_top.IbexDebugReqX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(debug_req_i)

ibex_top.IbexFetchEnableX

concurent assert

 
disable iff((!rst_ni)!=='0)! $isunknown(fetch_enable_i)

ibex_top.WaddrAZeroForDummyInstr

concurent assert

Dummy instructions may only write to register 0, which is a special register when dummy instructions are enabled.

disable iff((!rst_ni)!=='0)((dummy_instr_wb && rf_we_wb) |-> (rf_waddr_wb == '0))

ibex_top.CrashDumpCurrentPCConn

concurent assert

Ensure the crash dump is connected to the correct internal signals

disable iff((!rst_ni)!=='0)(crash_dump_o.current_pc === u_ibex_core.pc_id)

ibex_top.CrashDumpNextPCConn

concurent assert

 
disable iff((!rst_ni)!=='0)(crash_dump_o.next_pc === u_ibex_core.pc_if)

ibex_top.CrashDumpLastDataAddrConn

concurent assert

 
disable iff((!rst_ni)!=='0)(crash_dump_o.last_data_addr === u_ibex_core.load_store_unit_i.addr_last_q)

ibex_top.CrashDumpExceptionPCConn

concurent assert

 
disable iff((!rst_ni)!=='0)(crash_dump_o.exception_pc === u_ibex_core.cs_registers_i.mepc_q)

ibex_top.CrashDumpExceptionAddrConn

concurent assert

 
disable iff((!rst_ni)!=='0)(crash_dump_o.exception_addr === u_ibex_core.cs_registers_i.mtval_q)

ibex_top.MajorAlertOnDMemIntegrityErr

concurent assert

 
disable iff((!rst_ni)!=='0)((data_rvalid_i && | data_ecc_err) |-> (## [0 : 5] alert_major_bus_o))

ibex_top.MajorAlertOnIMemIntegrityErr

concurent assert

Check alerts from memory integrity failures

disable iff((!rst_ni)!=='0)((instr_rvalid_i && | instr_ecc_err) |-> (## [0 : 5] alert_major_bus_o))

Structs

typedef struct pending_access_t

Functions

insn_write_sync_exc_seen(logic[31:0] insn_bits)

Returns 1'b1 if the provided instruction decodes to one that would write the sync_exc_bit of the CPUCTRLSTS CSR

Parameters:

insn_bits (logic[31:0])

new_sync_exc_bit(logic[31:0] insn_bits, logic[31:0] rs1, logic cur_bit)

Given an instruction that writes the sync_exc_bit of the CPUCTRLSTS CSR along with the value of the rs1 register read for that instruction and the current predicted sync_exc_bit bit return the new value of the sync_exc_bit after the instruction is executed.

Parameters:

  • insn_bits (logic[31:0])

  • rs1 (logic[31:0])

  • cur_bit (logic)

Submodules

  • ibex_top

    • core_clock_gate_i : prim_clock_gating

    • g_clock_en_non_secure : [if !(SecureIbex)]

    • g_dside_tracker : [for (genvar i=0;i<MaxOutstandingDSideAccesses;i++)]

    • g_no_secure_ibex_mem_assert : [if !(SecureIbex)]

    • gen_no_lockstep : [if !(Lockstep)]

    • gen_no_mem_ecc : [if !(MemECC)]

    • gen_non_mem_rdata_ecc : [if !(MemECC)]

    • gen_norams : [if !(ICache)]

    • gen_noscramble : [if !(ICacheScramble)]

    • gen_regfile_ff : []

    • u_fetch_enable_buf : prim_buf

    • u_ibex_core : ibex_core

    • u_rf_rdata_a_ecc_buf : prim_buf

    • u_rf_rdata_b_ecc_buf : prim_buf

core_clock_gate_i (prim_clock_gating) u_fetch_enable_buf (prim_buf) u_ibex_core (ibex_core) u_rf_rdata_a_ecc_buf (prim_buf) u_rf_rdata_b_ecc_buf (prim_buf) g_clock_en_non_secure g_dside_tracker gen_regfile_ff.register_file_i (ibex_register_file_ff) gen_regfile_ff ibex_top

Flow Diagram of ibex_top

core_clock_gate_i (prim_clock_gating) clk_i test_en_i clk_o u_fetch_enable_buf (prim_buf) in_i out_o u_ibex_core (ibex_core) clk_i rst_ni hart_id_i boot_addr_i instr_req_o instr_gnt_i instr_rvalid_i instr_addr_o instr_err_i data_req_o data_gnt_i data_rvalid_i data_we_o data_be_o data_addr_o data_err_i dummy_instr_id_o dummy_instr_wb_o rf_raddr_a_o rf_raddr_b_o rf_waddr_wb_o rf_we_wb_o rf_wdata_wb_ecc_o rf_rdata_a_ecc_i rf_rdata_b_ecc_i irq_software_i irq_timer_i irq_external_i irq_fast_i irq_nm_i debug_req_i crash_dump_o double_fault_seen_o rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr rvfi_mode rvfi_ixl rvfi_rs1_addr rvfi_rs2_addr rvfi_rs3_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rs3_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata rvfi_ext_pre_mip rvfi_ext_post_mip rvfi_ext_nmi rvfi_ext_nmi_int rvfi_ext_debug_req rvfi_ext_debug_mode rvfi_ext_rf_wr_suppress rvfi_ext_mcycle rvfi_ext_mhpmcounters rvfi_ext_mhpmcountersh rvfi_ext_ic_scr_key_valid rvfi_ext_irq_valid fetch_enable_i u_rf_rdata_a_ecc_buf (prim_buf) in_i out_o u_rf_rdata_b_ecc_buf (prim_buf) in_i out_o g_clock_en_non_secure g_track_first_entry g_track_other_entries g_dside_tracker gen_no_lockstep gen_no_mem_ecc gen_non_mem_rdata_ecc gen_norams gen_noscramble gen_regfile_ff.register_file_i (ibex_register_file_ff) clk_i rst_ni test_en_i dummy_instr_id_i dummy_instr_wb_i raddr_a_i rdata_a_o raddr_b_i rdata_b_o waddr_a_i wdata_a_i we_a_i gen_regfile_ff ibex_top clk_i rst_ni test_en_i hart_id_i boot_addr_i instr_req_o instr_gnt_i instr_rvalid_i instr_addr_o instr_err_i data_req_o data_gnt_i data_rvalid_i data_we_o data_be_o data_addr_o data_err_i irq_software_i irq_timer_i irq_external_i irq_fast_i irq_nm_i debug_req_i crash_dump_o double_fault_seen_o rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr rvfi_mode rvfi_ixl rvfi_rs1_addr rvfi_rs2_addr rvfi_rs3_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rs3_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata rvfi_ext_pre_mip rvfi_ext_post_mip rvfi_ext_nmi rvfi_ext_nmi_int rvfi_ext_debug_req rvfi_ext_debug_mode rvfi_ext_rf_wr_suppress rvfi_ext_mcycle rvfi_ext_mhpmcounters rvfi_ext_mhpmcountersh rvfi_ext_ic_scr_key_valid rvfi_ext_irq_valid fetch_enable_i

Sub-Instances Diagram of ibex_top

core_clock_gate_i (prim_clock_gating) clk_i en_i test_en_i clk_o u_fetch_enable_buf (prim_buf) in_i out_o u_ibex_core (ibex_core) clk_i rst_ni hart_id_i boot_addr_i instr_req_o instr_gnt_i instr_rvalid_i instr_addr_o instr_rdata_i instr_err_i data_req_o data_gnt_i data_rvalid_i data_we_o data_be_o data_addr_o data_wdata_o data_rdata_i data_err_i dummy_instr_id_o dummy_instr_wb_o rf_raddr_a_o rf_raddr_b_o rf_waddr_wb_o rf_we_wb_o rf_wdata_wb_ecc_o rf_rdata_a_ecc_i rf_rdata_b_ecc_i ic_tag_req_o ic_tag_write_o ic_tag_addr_o ic_tag_wdata_o ic_tag_rdata_i ic_data_req_o ic_data_write_o ic_data_addr_o ic_data_wdata_o ic_data_rdata_i ic_scr_key_valid_i ic_scr_key_req_o irq_software_i irq_timer_i irq_external_i irq_fast_i irq_nm_i irq_pending_o debug_req_i crash_dump_o double_fault_seen_o rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr rvfi_mode rvfi_ixl rvfi_rs1_addr rvfi_rs2_addr rvfi_rs3_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rs3_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata rvfi_ext_pre_mip rvfi_ext_post_mip rvfi_ext_nmi rvfi_ext_nmi_int rvfi_ext_debug_req rvfi_ext_debug_mode rvfi_ext_rf_wr_suppress rvfi_ext_mcycle rvfi_ext_mhpmcounters rvfi_ext_mhpmcountersh rvfi_ext_ic_scr_key_valid rvfi_ext_irq_valid fetch_enable_i alert_minor_o alert_major_internal_o alert_major_bus_o core_busy_o u_rf_rdata_a_ecc_buf (prim_buf) in_i out_o u_rf_rdata_b_ecc_buf (prim_buf) in_i out_o core_sleep_o clock_en data_rdata_core data_rdata_i instr_rdata_core instr_rdata_i data_wdata_o data_wdata_core icache_alert_major_internal icache_tag_alert icache_data_alert alert_major_internal_o core_alert_major_internal lockstep_alert_major_internal rf_alert_major_internal icache_alert_major_internal alert_major_bus_o core_alert_major_bus lockstep_alert_major_bus alert_minor_o core_alert_minor lockstep_alert_minor new_sync_exc rvfi_valid rvfi_trap rvfi_ext_debug_mode double_fault_seen_predicted sync_exc_seen new_sync_exc double_fault_seen_delay_buffer double_fault_seen_o double_fault_seen_delay_buffer_q double_fault_seen_delay_buffer_q rst_ni clk_i double_fault_seen_delay_buffer sync_exc_seen new_sync_exc rvfi_valid rvfi_insn insn_bits rs1 rvfi_rs1_rdata cur_bit sync_exc_seen clock_en core_busy_q debug_req_i irq_pending irq_nm_i unused_core_busy core_busy_q core_busy_q rst_ni clk_i core_busy_d g_clock_en_non_secure pending_dside_accesses_shifted pending_dside_accesses_q data_rvalid_i pending_dside_accesses_q rst_ni clk pending_dside_accesses_d pending_dside_accesses_d pending_dside_accesses_shifted pending_dside_accesses_d.valid data_req_o data_gnt_i pending_dside_accesses_shifted.valid pending_dside_accesses_d.is_read data_we_o g_track_first_entry pending_dside_accesses_d pending_dside_accesses_shifted pending_dside_accesses_d.valid data_req_o data_gnt_i pending_dside_accesses_shifted.valid pending_dside_accesses_d.is_read data_we_o g_track_other_entries g_dside_tracker lockstep_alert_major_internal lockstep_alert_major_bus lockstep_alert_minor unused_scan scan_rst_ni gen_no_lockstep data_wdata_intg_o gen_no_mem_ecc unused_intg data_rdata_intg_i instr_rdata_intg_i gen_non_mem_rdata_ecc unused_ram_cfg ram_cfg_i unused_ram_inputs ic_tag_req ic_tag_write ic_tag_addr ic_tag_wdata ic_data_req ic_data_write ic_data_addr ic_data_wdata scramble_key_q scramble_nonce_q scramble_key_valid_q scramble_key_valid_d ic_tag_rdata ic_data_rdata icache_tag_alert icache_data_alert gen_norams unused_scramble_inputs scramble_key_valid_i scramble_key_i scramble_nonce_i scramble_req_q ic_scr_key_req scramble_key_valid_d scramble_req_d scramble_req_d scramble_req_q scramble_req_o scramble_key_q scramble_nonce_q scramble_key_valid_q scramble_key_valid_d gen_noscramble gen_regfile_ff.register_file_i (ibex_register_file_ff) clk_i rst_ni test_en_i dummy_instr_id_i dummy_instr_wb_i raddr_a_i rdata_a_o raddr_b_i rdata_b_o waddr_a_i wdata_a_i we_a_i err_o gen_regfile_ff ibex_top clk_i rst_ni test_en_i ram_cfg_i hart_id_i boot_addr_i instr_req_o instr_gnt_i instr_rvalid_i instr_addr_o instr_rdata_i instr_rdata_intg_i instr_err_i data_req_o data_gnt_i data_rvalid_i data_we_o data_be_o data_addr_o data_wdata_o data_wdata_intg_o data_rdata_i data_rdata_intg_i data_err_i irq_software_i irq_timer_i irq_external_i irq_fast_i irq_nm_i scramble_key_valid_i scramble_key_i scramble_nonce_i scramble_req_o debug_req_i crash_dump_o double_fault_seen_o rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr rvfi_mode rvfi_ixl rvfi_rs1_addr rvfi_rs2_addr rvfi_rs3_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rs3_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata rvfi_ext_pre_mip rvfi_ext_post_mip rvfi_ext_nmi rvfi_ext_nmi_int rvfi_ext_debug_req rvfi_ext_debug_mode rvfi_ext_rf_wr_suppress rvfi_ext_mcycle rvfi_ext_mhpmcounters rvfi_ext_mhpmcountersh rvfi_ext_ic_scr_key_valid rvfi_ext_irq_valid fetch_enable_i alert_minor_o alert_major_internal_o alert_major_bus_o core_sleep_o scan_rst_ni

Schematic Diagram of ibex_top