Class dv_lib_pkg::dv_base_vseq

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_transaction

      • uvm_pkg :: uvm_sequence_item

        • uvm_pkg :: uvm_sequence_base

          • uvm_pkg :: uvm_sequence

            • dv_lib_pkg :: dv_base_vseq

Collaboration Diagram of dv_base_vseq

Parameters

Name	Default value	Description
RAL_T	dv_base_reg_block
CFG_T	dv_base_env_cfg
COV_T	dv_base_env_cov
VIRTUAL_SEQUENCER_T	dv_base_virtual_sequencer

Variables

Name	Type	Description
num_trans	uint	number of iterations to run the test seq please override constraint in extended vseq randomization for this is disabled in pre_start since we don't want to re-randomize it again
cfg	dv_base_env_cfg#(dv_base_reg_block)	handles for ease of op
ral	dv_base_reg_block
cov	dv_base_env_cov#(dv_base_env_cfg#(dv_base_reg_block))
do_dut_init	bit	knobs to enable pre_start routines
do_apply_reset	bit
do_wait_for_reset	bit
do_dut_shutdown	bit	knobs to enable post_start routines
enable_asserts_in_hw_reset_rand_wr	bit	various knobs to enable certain routines this knob allows user to disable assertions in csr_hw_reset before random write sequence, the assertions will turn back on after the hw reset deasserted

Constraints

Name	Description
num_trans_c

Constructors

function

new(string name = "")

Parameters:

name (string)

Functions

virtual function void

set_handles()

virtual function void

configure_vseq()

This function is invoked in pre_randomize(). Override it in the extended classes to configure / control the randomization of this sequence.

virtual function void

set_csr_assert_en(bit enable, string path = "*")

enable/disable csr_assert

Parameters:

• enable (bit)

• path (string)

Tasks

virtual function

pre_start()

virtual function

body()

virtual function

post_start()

virtual function

dut_init(string reset_kind = "HARD")

startup, reset and shutdown related tasks

Parameters:

reset_kind (string)

virtual function

apply_reset(string kind = "HARD")

Parameters:

kind (string)

virtual function

apply_resets_concurrently(int reset_duration_ps = 0)

Apply all resets in the DUT concurrently to generate a random in-test reset scenario.

• Assert resets concurrently to make sure all resets are issued.
• Deassert resets concurrently is a specific requirement of the stress_all_with_rand_reset sequence, which will randomly issue resets and terminate the parallel sequence once all DUT resets are deasserted. If DUT resets are deasserted at different time, the parallel sequence might send a transaction request to driver between different resets are deasserting. Then when stress_all_with_rand_reset sequence tries to terminate the parallel sequence, an UVM_ERROR will be thrown by the sequencer saying task responsible for requesting a wait_for_grant has been killed. In order to ensure all resets at least being asserted for one clock cycle, this task takes an optional input reset_duration_ps if the DUT has additional resets. The task uses this input to compute the minimal time required to keep all resets asserted.

Parameters:

reset_duration_ps (int)

virtual function

post_apply_reset(string reset_kind = "HARD")

This is called after apply_reset in this class and after apply_resets_concurrently in cip_base_vseq::run_seq_with_rand_reset_vseq.

Parameters:

reset_kind (string)

virtual function

wait_for_reset(string reset_kind = "HARD", bit wait_for_assert = 1, bit wait_for_deassert = 1)

Parameters:

• reset_kind (string)

• wait_for_assert (bit)

• wait_for_deassert (bit)

virtual function

dut_shutdown()

DUT shutdown

this is called in post_start if do_dut_shutdown bit is set

virtual function

run_csr_vseq_wrapper(int num_times = 1, dv_base_reg_block models = {})

wrapper task around run_csr_vseq

the purpose is to be able to call this directly for actual csr tests (as opposed to higher level stress test that could also run csr seq as a fork by calling run_csr_vseq(..) task)

Parameters:

• num_times (int)

• models (dv_base_reg_block)

virtual function

run_csr_vseq(string csr_test_type, int num_test_csrs = 0, bit do_rand_wr_and_reset = 1, dv_base_reg_block models = {}, string ral_name = "")

capture the entire csr seq as a task that can be overridden if desired arg csr_test_type: what csr test to run {hw_reset, rw, bit_bash, aliasing} arg num_test_csrs:instead of testing the entire ral model or passing test chunk info via plusarg, provide ability to set a random number of csrs to test from higher level sequence models is the list of RAL models to run the common sequences on. ral_name is the string name of the RAL to run the common sequences on. Both of these inputs are 'null' by default. If externally set, models takes precedence over ral_name.

Parameters:

• csr_test_type (string)

• num_test_csrs (int)

• do_rand_wr_and_reset (bit)

• models (dv_base_reg_block)

• ral_name (string)

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