Interface ibex_mem_intf

ibex_mem_intf #( .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH), .INTG_WIDTH(INTG_WIDTH) ) u_ibex_mem_intf ( .clk(clk) );

Block Diagram of ibex_mem_intf

Parameters

Name	Default value	Description
ADDR_WIDTH	32
DATA_WIDTH	32
INTG_WIDTH	7

Ports

Name	Type	Direction	Description
clk	wire logic	input

Signals

Name	Type	Description
reset	wire
request	wire
grant	wire
addr	wire[ADDR_WIDTH-1:0]
we	wire
be	wire[DATA_WIDTH/8-1:0]
rvalid	wire
wdata	wire[DATA_WIDTH-1:0]
wintg	wire[INTG_WIDTH-1:0]
rdata	wire[DATA_WIDTH-1:0]
rintg	wire[INTG_WIDTH-1:0]
error	wire
misaligned_first	wire
misaligned_second	wire
misaligned_first_saw_error	wire
m_mode_access	wire
spurious_response	wire

Tasks

function

wait_clks(int num)

Parameters:

num (int)

function

wait_neg_clks(int num)

Parameters:

num (int)

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