[source]

Module ibex_controller

WritebackStageBranchPredictorMemECCclk_ilogicrst_nilogicillegal_insn_ilogicecall_insn_ilogicmret_insn_ilogicdret_insn_ilogicwfi_insn_ilogicebrk_insn_ilogiccsr_pipe_flush_ilogicinstr_valid_ilogicinstr_i[31:0]logicinstr_compressed_i[15:0]logicinstr_is_compressed_ilogicinstr_bp_taken_ilogicinstr_fetch_err_ilogicinstr_fetch_err_plus2_ilogicpc_id_i[31:0]logicinstr_exec_ilogiclsu_addr_last_i[31:0]logicload_err_ilogicstore_err_ilogicmem_resp_intg_err_ilogicbranch_set_ilogicbranch_not_set_ilogicjump_set_ilogiccsr_mstatus_mie_ilogicirq_pending_ilogicirqs_iibex_pkg::irqs_tirq_nm_ext_ilogicdebug_req_ilogicdebug_single_step_ilogicdebug_ebreakm_ilogicdebug_ebreaku_ilogictrigger_match_ilogicpriv_mode_iibex_pkg::priv_lvl_estall_id_ilogicstall_wb_ilogicready_wb_ilogicctrl_busy_ologicinstr_valid_clear_ologicid_in_ready_ologiccontroller_run_ologicinstr_req_ologicpc_set_ologicpc_mux_oibex_pkg::pc_sel_ent_branch_mispredict_ologicexc_pc_mux_oibex_pkg::exc_pc_sel_eexc_cause_oibex_pkg::exc_cause_twb_exception_ologicid_exception_ologicnmi_mode_ologicdebug_cause_oibex_pkg::dbg_cause_edebug_csr_save_ologicdebug_mode_ologicdebug_mode_entering_ologiccsr_save_if_ologiccsr_save_id_ologiccsr_save_wb_ologiccsr_restore_mret_id_ologiccsr_restore_dret_id_ologiccsr_save_cause_ologiccsr_mtval_ologic[31:0]flush_id_ologicperf_jump_ologicperf_tbranch_ologic

Block Diagram of ibex_controller

Parameters

Name

Default

Description
WritebackStage

1'b0
BranchPredictor

1'b0
MemECC

1'b0
Ports

Name

Type

Direction

Description
clk_i

wire logic

input
rst_ni

wire logic

input
ctrl_busy_o

var logic

output

core is busy processing instrs
illegal_insn_i

wire logic

input

decoder related signals decoder has an invalid instr
ecall_insn_i

wire logic

input

decoder has ECALL instr
mret_insn_i

wire logic

input

decoder has MRET instr
dret_insn_i

wire logic

input

decoder has DRET instr
wfi_insn_i

wire logic

input

decoder has WFI instr
ebrk_insn_i

wire logic

input

decoder has EBREAK instr
csr_pipe_flush_i

wire logic

input

do CSR-related pipeline flush
instr_valid_i

wire logic

input

instr from IF-ID pipeline stage instr is valid
instr_i

wire logic [31 : 0]

input

uncompressed instr data for mtval
instr_compressed_i

wire logic [15 : 0]

input

instr compressed data for mtval
instr_is_compressed_i

wire logic

input

instr is compressed
instr_bp_taken_i

wire logic

input

instr was predicted taken branch
instr_fetch_err_i

wire logic

input

instr has error
instr_fetch_err_plus2_i

wire logic

input

instr error is x32
pc_id_i

wire logic [31 : 0]

input

instr address
instr_valid_clear_o

var logic

output

to IF-ID pipeline stage kill instr in IF-ID reg
id_in_ready_o

var logic

output

ID stage is ready for new instr
controller_run_o

var logic

output

Controller is in standard instruction
instr_exec_i

wire logic

input

run mode Execution control, when clear ID/EX
instr_req_o

var logic

output

stage stops accepting instructions from IF to prefetcher start fetching instructions
pc_set_o

var logic

output

jump to address set by pc_mux
pc_mux_o

var ibex_pkg::pc_sel_e

output

IF stage fetch address selector
nt_branch_mispredict_o

var logic

output

(boot, normal, exception...) Not-taken branch in ID/EX was
exc_pc_mux_o

var ibex_pkg::exc_pc_sel_e

output

mispredicted (predicted taken) IF stage selector for exception PC
exc_cause_o

var ibex_pkg::exc_cause_t

output

for IF stage, CSRs
lsu_addr_last_i

wire logic [31 : 0]

input

LSU for mtval
load_err_i

wire logic

input
store_err_i

wire logic

input
mem_resp_intg_err_i

wire logic

input
wb_exception_o

var logic

output

Instruction in WB taking an exception
id_exception_o

var logic

output

Instruction in ID taking an exception
branch_set_i

wire logic

input

jump/branch signals branch set signal (branch definitely
branch_not_set_i

wire logic

input

taken) branch is definitely not taken
jump_set_i

wire logic

input

jump taken set signal
csr_mstatus_mie_i

wire logic

input

interrupt signals M-mode interrupt enable bit
irq_pending_i

wire logic

input

interrupt request pending
irqs_i

wire ibex_pkg::irqs_t

input

interrupt requests qualified with
irq_nm_ext_i

wire logic

input

mie CSR non-maskeable interrupt
nmi_mode_o

var logic

output

core executing NMI handler
debug_req_i

wire logic

input

debug signals
debug_cause_o

var ibex_pkg::dbg_cause_e

output
debug_csr_save_o

var logic

output
debug_mode_o

var logic

output
debug_mode_entering_o

var logic

output
debug_single_step_i

wire logic

input
debug_ebreakm_i

wire logic

input
debug_ebreaku_i

wire logic

input
trigger_match_i

wire logic

input
csr_save_if_o

var logic

output
csr_save_id_o

var logic

output
csr_save_wb_o

var logic

output
csr_restore_mret_id_o

var logic

output
csr_restore_dret_id_o

var logic

output
csr_save_cause_o

var logic

output
csr_mtval_o

var logic [31 : 0]

output
priv_mode_i

wire ibex_pkg::priv_lvl_e

input
stall_id_i

wire logic

input

stall & flush signals
stall_wb_i

wire logic

input
flush_id_o

var logic

output
ready_wb_i

wire logic

input
perf_jump_o

var logic

output

performance monitors we are executing a jump
perf_tbranch_o

var logic

output

instruction (j, jr, jal, jalr) we are executing a taken branch
Assertions

Name

Kind

Description

ibex_controller.IllegalInsnOnlyIfInsnValid

concurent assert

 
disable iff((!rst_ni)!=='0)(illegal_insn_i |-> instr_valid_i)

ibex_controller.IbexExceptionPrioOnehot

concurent assert

 
disable iff((!rst_ni)!=='0)(((ctrl_fsm_cs == FLUSH) & exc_req_q) |-> $onehot({instr_fetch_err_prio, illegal_insn_prio, ecall_insn_prio, ebrk_insn_prio, store_err_prio, load_err_prio}))

ibex_controller.PipeEmptyOnIrq

concurent assert

 
disable iff((!rst_ni)!=='0)(((ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN)) |-> (~ instr_valid_i & ready_wb_i))

ibex_controller.AlwaysInstrClearOnMispredict

concurent assert

////////////// Assertions // //////////////

disable iff((!rst_ni)!=='0)(nt_branch_mispredict_o |-> instr_valid_clear_o)

ibex_controller.IbexCtrlStateValid

concurent assert

Selectors must be known/valid.

disable iff((!rst_ni)!=='0)(ctrl_fsm_cs inside {RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH, IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID})

ibex_controller.IbexPipelineFlushOnChangingDebugMode

concurent assert

If entering or exiting debug mode, the pipeline must be flushed. This is because Ibex currently does not support some of the pipeline stages being in debug mode; either all or none of the pipeline stages must be in debug mode. As flush_id_o only affects the ID/EX stage but does not prevent a fetched instruction from proceeding to ID/EX the next cycle, the assertion additionally requires pc_set_o, which sets the PC in the IF stage to a new value, hence preventing a fetched instruction from proceeding to the ID/EX stage in the next cycle.

disable iff((!rst_ni)!=='0)((debug_mode_d != debug_mode_q) |-> (flush_id_o & pc_set_o))

Always Blocks

always_ff @(negedge clk_i)

synopsys translate_off make sure we are called later so that we do not generate messages for glitches

always_comb @()

generate ID of fast interrupts, highest priority to lowest ID

always_comb @()

Core controller

always_ff @(posedge clk_i or negedge rst_ni)

update registers

RESET RESET BOOT_SET BOOT_SET FIRST_FETCH FIRST_FETCH DECODE DECODE DBG_TAKEN_IF DBG_TAKEN_IF IRQ_TAKEN IRQ_TAKEN FLUSH FLUSH DBG_TAKEN_ID DBG_TAKEN_ID WAIT_SLEEP WAIT_SLEEP SLEEP SLEEP 1 [EMPTY] 2 [EMPTY] 3 [(id_in_ready_o)] 5 [(enter_debug_mode)] 4 [(handle_irq)] 6 [((special_req) && (ready_wb_i | wb_exception_o))] 7 [((! stall && ! special_req && ! id_wb_pending) && (enter_debug_mode))] 8 [((! stall && ! special_req && ! id_wb_pending) && !(enter_debug_mode) && (handle_irq))] 10 [EMPTY] 9 [EMPTY] 11 [EMPTY] 12 [((exc_req_q || store_err_q || load_err_q) && (1'b1 == ebrk_insn_prio) && (debug_mode_q | ebreak_into_debug))] 13 [(!(exc_req_q || store_err_q || load_err_q) && !(mret_insn) && !(dret_insn) && (wfi_insn))] 14 [(enter_debug_mode_prio_q && ! ebrk_insn_prio && ebreak_into_debug)] 15 [EMPTY] 16 [EMPTY] 17 [(irq_nm || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i)]
FSM Transitions for ctrl_fsm_cs

#

Current State

Next State

Condition

Comment

1

RESET

BOOT_SET

[EMPTY]

2

BOOT_SET

FIRST_FETCH

[EMPTY]

3

FIRST_FETCH

DECODE

[(id_in_ready_o)]

4

FIRST_FETCH

IRQ_TAKEN

[(handle_irq)]

5

FIRST_FETCH

DBG_TAKEN_IF

[(enter_debug_mode)]

6

DECODE

FLUSH

[((special_req) && (ready_wb_i | wb_exception_o))]

7

DECODE

DBG_TAKEN_IF

[((! stall && ! special_req && ! id_wb_pending) && (enter_debug_mode))]

8

DECODE

IRQ_TAKEN

[((! stall && ! special_req && ! id_wb_pending) && !(enter_debug_mode) && (handle_irq))]

9

IRQ_TAKEN

DECODE

[EMPTY]

10

DBG_TAKEN_IF

DECODE

[EMPTY]

11

FLUSH

DECODE

[EMPTY]

12

FLUSH

DBG_TAKEN_ID

[((exc_req_q || store_err_q || load_err_q) && (1'b1 == ebrk_insn_prio) && (debug_mode_q | ebreak_into_debug))]

13

FLUSH

WAIT_SLEEP

[(!(exc_req_q || store_err_q || load_err_q) && !(mret_insn) && !(dret_insn) && (wfi_insn))]

14

FLUSH

DBG_TAKEN_IF

[(enter_debug_mode_prio_q && ! ebrk_insn_prio && ebreak_into_debug)]

15

DBG_TAKEN_ID

DECODE

[EMPTY]

16

WAIT_SLEEP

SLEEP

[EMPTY]

17

SLEEP

FIRST_FETCH

[(irq_nm || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i)]

Instances

Submodules

  • ibex_controller

    • g_no_intg_irq_int : [if !(MemECC)]

    • g_no_wb_exceptions : [if !(WritebackStage)]