Module prim_onehot_mux

prim_onehot_mux #( .Width(Width), .Inputs(Inputs) ) u_prim_onehot_mux ( .clk_i(clk_i), .rst_ni(rst_ni), .in_i(in_i), .sel_i(sel_i), .out_o(out_o) );

Block Diagram of prim_onehot_mux

Parameters

Name	Default	Description
Width	32
Inputs	8

Ports

Name	Type	Direction	Description
clk_i	wire logic	input	Clock and reset only for assertions
rst_ni	wire logic	input
in_i	wire logic [Width - 1 : 0]	input
sel_i	wire logic [Inputs - 1 : 0]	input	Must be one-hot or zero
out_o	var logic [Width - 1 : 0]	output

Assertions

Name	Kind	Description
prim_onehot_mux.SelIsOnehot_A	concurent assert	disable iff((!rst_ni)!=='0)$onehot0(sel_i)

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