[source]

Module ibex_counter

CounterWidthProvideValUpdclk_ilogicrst_nilogiccounter_inc_ilogiccounterh_we_ilogiccounter_we_ilogiccounter_val_i[31:0]logiccounter_val_ologic[63:0]counter_val_upd_ologic[63:0]

Block Diagram of ibex_counter

Parameters

Name

Default

Description

CounterWidth

32

ProvideValUpd

0

When set counter_val_upd_o provides an incremented version of the counter value, otherwise the output is hard-wired to 0. This is required to allow Xilinx DSP inference to work correctly. When ProvideValUpd is set no DSPs are inferred.

Ports

Name

Type

Direction

Description

clk_i

wire logic

input

rst_ni

wire logic

input

counter_inc_i

wire logic

input

counterh_we_i

wire logic

input

counter_we_i

wire logic

input

counter_val_i

wire logic [31 : 0]

input

counter_val_o

var logic [63 : 0]

output

counter_val_upd_o

var logic [63 : 0]

output

Always Blocks

always_comb @()

Update

Instances

Submodules

  • ibex_counter
    • g_cnt_no_dsp : [if !(UseDsp=="yes")]

    • g_counter_full : [if !(CounterWidth<64)]