Package ibex_pkg
Name |
Actual Type |
Description |
---|---|---|
ibex_mubi_t |
logic[IbexMuBiWidth-1:0] |
|
lfsr_perm_t |
logic[LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] |
|
lfsr_seed_t |
logic[LfsrWidth-1:0] |
Enums
- alu_op_e
- Enum Items:
ALU_ADD
Arithmetics
ALU_SUB
ALU_XOR
Logics
ALU_OR
ALU_AND
ALU_XNOR
RV32B
ALU_ORN
ALU_ANDN
ALU_SRA
Shifts
ALU_SRL
ALU_SLL
ALU_SRO
RV32B
ALU_SLO
ALU_ROR
ALU_ROL
ALU_GREV
ALU_GORC
ALU_SHFL
ALU_UNSHFL
ALU_XPERM_N
ALU_XPERM_B
ALU_XPERM_H
ALU_SH1ADD
Address Calculations RV32B
ALU_SH2ADD
ALU_SH3ADD
ALU_LT
Comparisons
ALU_LTU
ALU_GE
ALU_GEU
ALU_EQ
ALU_NE
ALU_MIN
RV32B
ALU_MINU
ALU_MAX
ALU_MAXU
ALU_PACK
Pack RV32B
ALU_PACKU
ALU_PACKH
ALU_SEXTB
Sign-Extend RV32B
ALU_SEXTH
ALU_CLZ
Bitcounting RV32B
ALU_CTZ
ALU_CPOP
ALU_SLT
Set lower than
ALU_SLTU
ALU_CMOV
Ternary Bitmanip Operations RV32B
ALU_CMIX
ALU_FSL
ALU_FSR
ALU_BSET
Single-Bit Operations RV32B
ALU_BCLR
ALU_BINV
ALU_BEXT
ALU_BCOMPRESS
Bit Compress / Decompress RV32B
ALU_BDECOMPRESS
ALU_BFP
Bit Field Place RV32B
ALU_CLMUL
Carry-less Multiply RV32B
ALU_CLMULR
ALU_CLMULH
ALU_CRC32_B
Cyclic Redundancy Check
ALU_CRC32C_B
ALU_CRC32_H
ALU_CRC32C_H
ALU_CRC32_W
ALU_CRC32C_W
- csr_num_e
CSRs
- Enum Items:
CSR_MVENDORID = 12'hF11
Machine information
CSR_MARCHID = 12'hF12
CSR_MIMPID = 12'hF13
CSR_MHARTID = 12'hF14
CSR_MCONFIGPTR = 12'hF15
CSR_MSTATUS = 12'h300
Machine trap setup
CSR_MISA = 12'h301
CSR_MIE = 12'h304
CSR_MTVEC = 12'h305
CSR_MCOUNTEREN = 12'h306
CSR_MSTATUSH = 12'h310
CSR_MENVCFG = 12'h30A
CSR_MENVCFGH = 12'h31A
CSR_MSCRATCH = 12'h340
Machine trap handling
CSR_MEPC = 12'h341
CSR_MCAUSE = 12'h342
CSR_MTVAL = 12'h343
CSR_MIP = 12'h344
CSR_PMPCFG0 = 12'h3A0
Physical memory protection
CSR_PMPCFG1 = 12'h3A1
CSR_PMPCFG2 = 12'h3A2
CSR_PMPCFG3 = 12'h3A3
CSR_PMPADDR0 = 12'h3B0
CSR_PMPADDR1 = 12'h3B1
CSR_PMPADDR2 = 12'h3B2
CSR_PMPADDR3 = 12'h3B3
CSR_PMPADDR4 = 12'h3B4
CSR_PMPADDR5 = 12'h3B5
CSR_PMPADDR6 = 12'h3B6
CSR_PMPADDR7 = 12'h3B7
CSR_PMPADDR8 = 12'h3B8
CSR_PMPADDR9 = 12'h3B9
CSR_PMPADDR10 = 12'h3BA
CSR_PMPADDR11 = 12'h3BB
CSR_PMPADDR12 = 12'h3BC
CSR_PMPADDR13 = 12'h3BD
CSR_PMPADDR14 = 12'h3BE
CSR_PMPADDR15 = 12'h3BF
CSR_SCONTEXT = 12'h5A8
CSR_MSECCFG = 12'h747
ePMP control
CSR_MSECCFGH = 12'h757
CSR_TSELECT = 12'h7A0
Debug trigger
CSR_TDATA1 = 12'h7A1
CSR_TDATA2 = 12'h7A2
CSR_TDATA3 = 12'h7A3
CSR_MCONTEXT = 12'h7A8
CSR_MSCONTEXT = 12'h7AA
CSR_DCSR = 12'h7b0
Debug/trace
CSR_DPC = 12'h7b1
CSR_DSCRATCH0 = 12'h7b2
Debug optional
CSR_DSCRATCH1 = 12'h7b3
optional
CSR_MCOUNTINHIBIT = 12'h320
Machine Counter/Timers
CSR_MHPMEVENT3 = 12'h323
CSR_MHPMEVENT4 = 12'h324
CSR_MHPMEVENT5 = 12'h325
CSR_MHPMEVENT6 = 12'h326
CSR_MHPMEVENT7 = 12'h327
CSR_MHPMEVENT8 = 12'h328
CSR_MHPMEVENT9 = 12'h329
CSR_MHPMEVENT10 = 12'h32A
CSR_MHPMEVENT11 = 12'h32B
CSR_MHPMEVENT12 = 12'h32C
CSR_MHPMEVENT13 = 12'h32D
CSR_MHPMEVENT14 = 12'h32E
CSR_MHPMEVENT15 = 12'h32F
CSR_MHPMEVENT16 = 12'h330
CSR_MHPMEVENT17 = 12'h331
CSR_MHPMEVENT18 = 12'h332
CSR_MHPMEVENT19 = 12'h333
CSR_MHPMEVENT20 = 12'h334
CSR_MHPMEVENT21 = 12'h335
CSR_MHPMEVENT22 = 12'h336
CSR_MHPMEVENT23 = 12'h337
CSR_MHPMEVENT24 = 12'h338
CSR_MHPMEVENT25 = 12'h339
CSR_MHPMEVENT26 = 12'h33A
CSR_MHPMEVENT27 = 12'h33B
CSR_MHPMEVENT28 = 12'h33C
CSR_MHPMEVENT29 = 12'h33D
CSR_MHPMEVENT30 = 12'h33E
CSR_MHPMEVENT31 = 12'h33F
CSR_MCYCLE = 12'hB00
CSR_MINSTRET = 12'hB02
CSR_MHPMCOUNTER3 = 12'hB03
CSR_MHPMCOUNTER4 = 12'hB04
CSR_MHPMCOUNTER5 = 12'hB05
CSR_MHPMCOUNTER6 = 12'hB06
CSR_MHPMCOUNTER7 = 12'hB07
CSR_MHPMCOUNTER8 = 12'hB08
CSR_MHPMCOUNTER9 = 12'hB09
CSR_MHPMCOUNTER10 = 12'hB0A
CSR_MHPMCOUNTER11 = 12'hB0B
CSR_MHPMCOUNTER12 = 12'hB0C
CSR_MHPMCOUNTER13 = 12'hB0D
CSR_MHPMCOUNTER14 = 12'hB0E
CSR_MHPMCOUNTER15 = 12'hB0F
CSR_MHPMCOUNTER16 = 12'hB10
CSR_MHPMCOUNTER17 = 12'hB11
CSR_MHPMCOUNTER18 = 12'hB12
CSR_MHPMCOUNTER19 = 12'hB13
CSR_MHPMCOUNTER20 = 12'hB14
CSR_MHPMCOUNTER21 = 12'hB15
CSR_MHPMCOUNTER22 = 12'hB16
CSR_MHPMCOUNTER23 = 12'hB17
CSR_MHPMCOUNTER24 = 12'hB18
CSR_MHPMCOUNTER25 = 12'hB19
CSR_MHPMCOUNTER26 = 12'hB1A
CSR_MHPMCOUNTER27 = 12'hB1B
CSR_MHPMCOUNTER28 = 12'hB1C
CSR_MHPMCOUNTER29 = 12'hB1D
CSR_MHPMCOUNTER30 = 12'hB1E
CSR_MHPMCOUNTER31 = 12'hB1F
CSR_MCYCLEH = 12'hB80
CSR_MINSTRETH = 12'hB82
CSR_MHPMCOUNTER3H = 12'hB83
CSR_MHPMCOUNTER4H = 12'hB84
CSR_MHPMCOUNTER5H = 12'hB85
CSR_MHPMCOUNTER6H = 12'hB86
CSR_MHPMCOUNTER7H = 12'hB87
CSR_MHPMCOUNTER8H = 12'hB88
CSR_MHPMCOUNTER9H = 12'hB89
CSR_MHPMCOUNTER10H = 12'hB8A
CSR_MHPMCOUNTER11H = 12'hB8B
CSR_MHPMCOUNTER12H = 12'hB8C
CSR_MHPMCOUNTER13H = 12'hB8D
CSR_MHPMCOUNTER14H = 12'hB8E
CSR_MHPMCOUNTER15H = 12'hB8F
CSR_MHPMCOUNTER16H = 12'hB90
CSR_MHPMCOUNTER17H = 12'hB91
CSR_MHPMCOUNTER18H = 12'hB92
CSR_MHPMCOUNTER19H = 12'hB93
CSR_MHPMCOUNTER20H = 12'hB94
CSR_MHPMCOUNTER21H = 12'hB95
CSR_MHPMCOUNTER22H = 12'hB96
CSR_MHPMCOUNTER23H = 12'hB97
CSR_MHPMCOUNTER24H = 12'hB98
CSR_MHPMCOUNTER25H = 12'hB99
CSR_MHPMCOUNTER26H = 12'hB9A
CSR_MHPMCOUNTER27H = 12'hB9B
CSR_MHPMCOUNTER28H = 12'hB9C
CSR_MHPMCOUNTER29H = 12'hB9D
CSR_MHPMCOUNTER30H = 12'hB9E
CSR_MHPMCOUNTER31H = 12'hB9F
CSR_CPUCTRLSTS = 12'h7C0
CSR_SECURESEED = 12'h7C1
- csr_op_e
CSR operations
- Enum Items:
CSR_OP_READ
CSR_OP_WRITE
CSR_OP_SET
CSR_OP_CLEAR
- ctrl_fsm_e
Controller FSM state encoding
- Enum Items:
RESET
BOOT_SET
WAIT_SLEEP
SLEEP
FIRST_FETCH
DECODE
FLUSH
IRQ_TAKEN
DBG_TAKEN_IF
DBG_TAKEN_ID
- dbg_cause_e
Debug cause
- Enum Items:
DBG_CAUSE_NONE = 3'h0
DBG_CAUSE_EBREAK = 3'h1
DBG_CAUSE_TRIGGER = 3'h2
DBG_CAUSE_HALTREQ = 3'h3
DBG_CAUSE_STEP = 3'h4
- exc_pc_sel_e
Exception PC mux selection
- Enum Items:
EXC_PC_EXC
EXC_PC_IRQ
EXC_PC_DBD
EXC_PC_DBG_EXC
Exception while in debug mode
- imm_a_sel_e
Immediate a selection
- Enum Items:
IMM_A_Z
IMM_A_ZERO
- imm_b_sel_e
Immediate b selection
- Enum Items:
IMM_B_I
IMM_B_S
IMM_B_B
IMM_B_U
IMM_B_J
IMM_B_INCR_PC
IMM_B_INCR_ADDR
- md_op_e
- Enum Items:
MD_OP_MULL
Multiplier/divider
MD_OP_MULH
MD_OP_DIV
MD_OP_REM
- nmi_int_cause_e
Internal NMI cause
- Enum Items:
NMI_INT_CAUSE_ECC = 5'b0
- op_a_sel_e
Operand a selection
- Enum Items:
OP_A_REG_A
OP_A_FWD
OP_A_CURRPC
OP_A_IMM
- op_b_sel_e
Operand b selection
- Enum Items:
OP_B_REG_B
OP_B_IMM
- opcode_e
/////////// Opcodes // ///////////
- Enum Items:
OPCODE_LOAD = 7'h03
OPCODE_MISC_MEM = 7'h0f
OPCODE_OP_IMM = 7'h13
OPCODE_AUIPC = 7'h17
OPCODE_STORE = 7'h23
OPCODE_OP = 7'h33
OPCODE_LUI = 7'h37
OPCODE_BRANCH = 7'h63
OPCODE_JALR = 7'h67
OPCODE_JAL = 7'h6f
OPCODE_SYSTEM = 7'h73
- pc_sel_e
PC mux selection
- Enum Items:
PC_BOOT
PC_JUMP
PC_EXC
PC_ERET
PC_DRET
PC_BP
- pmp_cfg_mode_e
PMP cfg structures
- Enum Items:
PMP_MODE_OFF = 2'b00
PMP_MODE_TOR = 2'b01
PMP_MODE_NA4 = 2'b10
PMP_MODE_NAPOT = 2'b11
- pmp_req_e
- Enum Items:
PMP_ACC_EXEC = 2'b00
PMP_ACC_WRITE = 2'b01
PMP_ACC_READ = 2'b10
- priv_lvl_e
Privileged mode
- Enum Items:
PRIV_LVL_M = 2'b11
PRIV_LVL_H = 2'b10
PRIV_LVL_S = 2'b01
PRIV_LVL_U = 2'b00
- regfile_e
/////////////////// Parameter Enums // ///////////////////
- Enum Items:
RegFileFF = 0
RegFileFPGA = 1
RegFileLatch = 2
- rf_wd_sel_e
Regfile write data selection
- Enum Items:
RF_WD_EX
RF_WD_CSR
- rv32b_e
- Enum Items:
RV32BNone = 0
RV32BBalanced = 1
RV32BOTEarlGrey = 2
RV32BFull = 3
- rv32m_e
- Enum Items:
RV32MNone = 0
RV32MSlow = 1
RV32MFast = 2
RV32MSingleCycle = 3
- wb_instr_type_e
Type of instruction present in writeback stage
- Enum Items:
WB_INSTR_LOAD
Instruction is awaiting load data
WB_INSTR_STORE
Instruction is awaiting store response
WB_INSTR_OTHER
Instruction doesn't fit into above categories
- x_debug_ver_e
Constants for the dcsr.xdebugver fields
- Enum Items:
XDEBUGVER_NO = 4'd0
no external debug support
XDEBUGVER_STD = 4'd4
external debug according to RISC-V debug spec
XDEBUGVER_NONSTD = 4'd15
debug not conforming to RISC-V debug spec
Structs
- typedef struct packed core2rf_t
Name |
Type |
Position |
Size |
---|---|---|---|
raddr_b |
logic[4:0] |
0 |
5 |
we_a |
logic |
5 |
1 |
waddr_a |
logic[4:0] |
6 |
5 |
raddr_a |
logic[4:0] |
11 |
5 |
dummy_instr_id |
logic |
16 |
1 |
- typedef struct packed crash_dump_t
////////////// IO Structs // //////////////
Name |
Type |
Position |
Size |
---|---|---|---|
exception_addr |
logic[31:0] |
0 |
32 |
exception_pc |
logic[31:0] |
32 |
32 |
last_data_addr |
logic[31:0] |
64 |
32 |
next_pc |
logic[31:0] |
96 |
32 |
current_pc |
logic[31:0] |
128 |
32 |
- typedef struct packed exc_cause_t
lower_cause irq_ext irq_int 6 5 4 0 struct union enum field
Name |
Type |
Position |
Size |
---|---|---|---|
lower_cause |
logic[4:0] |
0 |
5 |
irq_ext |
logic |
5 |
1 |
irq_int |
logic |
6 |
1 |
- typedef struct packed irqs_t
Interrupt requests
irq_fast irq_... irq_... irq_... 17 16 15 14 0 struct union enum field
Name |
Type |
Position |
Size |
---|---|---|---|
irq_fast |
logic[14:0] |
0 |
15 |
irq_external |
logic |
15 |
1 |
irq_timer |
logic |
16 |
1 |
irq_software |
logic |
17 |
1 |
- typedef struct packed pmp_cfg_t
read write exec mode lock 5 4 3 2 1 0 struct union enum field
Name |
Type |
Position |
Size |
---|---|---|---|
read |
logic |
0 |
1 |
write |
logic |
1 |
1 |
exec |
logic |
2 |
1 |
mode |
pmp_cfg_mode_e |
3 |
2 |
lock |
logic |
5 |
1 |
- typedef struct packed pmp_mseccfg_t
Machine Security Configuration (ePMP)
mml mmwp rlb 2 1 0 struct union enum field
Name |
Type |
Position |
Size |
---|---|---|---|
mml |
logic |
0 |
1 |
mmwp |
logic |
1 |
1 |
rlb |
logic |
2 |
1 |
////////////////// ALU operations // //////////////////