Module ibex_register_file_fpga

ibex_register_file_fpga #( .RV32E(RV32E), .DataWidth(DataWidth), .DummyInstructions(DummyInstructions), .WrenCheck(WrenCheck), .RdataMuxCheck(RdataMuxCheck), .WordZeroVal(WordZeroVal) ) u_ibex_register_file_fpga ( .clk_i(clk_i), .rst_ni(rst_ni), .test_en_i(test_en_i), .dummy_instr_id_i(dummy_instr_id_i), .dummy_instr_wb_i(dummy_instr_wb_i), .raddr_a_i(raddr_a_i), .rdata_a_o(rdata_a_o), .raddr_b_i(raddr_b_i), .rdata_b_o(rdata_b_o), .waddr_a_i(waddr_a_i), .wdata_a_i(wdata_a_i), .we_a_i(we_a_i), .err_o(err_o) );

Block Diagram of ibex_register_file_fpga

RISC-V register file

Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.

This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested.

Parameters

Name	Default	Description
RV32E	0
DataWidth	32
DummyInstructions	0
WrenCheck	0
RdataMuxCheck	0
WordZeroVal	'0

Ports

Name	Type	Direction	Description
clk_i	wire logic	input	Clock and Reset
rst_ni	wire logic	input
test_en_i	wire logic	input
dummy_instr_id_i	wire logic	input
dummy_instr_wb_i	wire logic	input
raddr_a_i	wire logic [4 : 0]	input	Read port R1
rdata_a_o	var logic [DataWidth - 1 : 0]	output
raddr_b_i	wire logic [4 : 0]	input	Read port R2
rdata_b_o	var logic [DataWidth - 1 : 0]	output
waddr_a_i	wire logic [4 : 0]	input	Write port W1
wdata_a_i	wire logic [DataWidth - 1 : 0]	input
we_a_i	wire logic	input
err_o	var logic	output	This indicates whether spurious WE or non-one-hot encoded raddr are detected.

Always Blocks

sync_write :

always @(posedge clk_i)

Note that the SystemVerilog LRM requires variables on the LHS of assignments within "always_ff" to not be written to by any other process. However, to enable the initialization of the inferred RAM32M primitives with non-zero values, below "initial" procedure is needed. Therefore, we use "always" instead of the generally preferred "always_ff" for the synchronous write procedure.

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