[source]

Module prim_generic_ram_1p

Block Diagram of prim_generic_ram_1p

Synchronous single-port SRAM model

Parameters
Name	Default	Description
Width	32	bit
Depth	128
DataBitsPerMask	1	Number of data bits per bit of write mask
MemInitFile	""	VMEM file to initialize the memory with

Ports
Name	Type	Direction	Description
clk_i	wire logic	input
req_i	wire logic	input
write_i	wire logic	input
addr_i	wire logic [Aw - 1 : 0]	input
wdata_i	wire logic [Width - 1 : 0]	input
wmask_i	wire logic [Width - 1 : 0]	input
rdata_o	var logic [Width - 1 : 0]	output	Read data. Data is returned one cycle after req_i is high.
cfg_i	wire ram_1p_cfg_t	input

Assertions
Name	Kind	Description
prim_generic_ram_1p.DataBitsPerMaskCheck_A	immediate assert	Width must be fully divisible by DataBitsPerMask ((Width % DataBitsPerMask) == 0)
prim_generic_ram_1p.MaskCheck_A	concurent assert	Ensure that all mask bits within a group have the same value for a write disable iff(('0)!=='0)((req_i && write_i) \|-> (wmask_i[k * DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0}))

Always Blocks

always @(posedge clk_i)

using always instead of always_ff to avoid 'ICPD

illegal combination of drivers' error thrown when using $readmemh system task to backdoor load an image

simutil_set_mem(int index, bit[311:0] val)

Function for setting a specific element in |mem| Returns 1 (true) for success, 0 (false) for errors.

Parameters:

simutil_get_mem(int index, bit[311:0] val)

Function for getting a specific element in |mem|

Parameters:

simutil_memload(string file)

Task for loading 'mem' with SystemVerilog system task $readmemh()