Module prim_ram_1p

prim_ram_1p #( .Width(Width), .Depth(Depth), .DataBitsPerMask(DataBitsPerMask), .MemInitFile(MemInitFile) ) u_prim_ram_1p ( .clk_i(clk_i), .cfg_i(cfg_i), .req_i(req_i), .write_i(write_i), .addr_i(addr_i), .wdata_i(wdata_i), .wmask_i(wmask_i), .rdata_o(rdata_o) );

Block Diagram of prim_ram_1p

Abstract primitives wrapper.

This file is a stop-gap until the DV file list is generated by FuseSoC. Its contents are taken from the file which would be generated by FuseSoC. https://github.com/lowRISC/ibex/issues/893

Parameters

Name	Default	Description
Width	32	bit
Depth	128
DataBitsPerMask	1	Number of data bits per bit of write mask
MemInitFile	""	VMEM file to initialize the memory width

Ports

Name	Type	Direction	Description
clk_i	wire logic	input
cfg_i	wire ram_1p_cfg_t	input
req_i	wire logic	input
write_i	wire logic	input
addr_i	wire logic [Aw - 1 : 0]	input
wdata_i	wire logic [Width - 1 : 0]	input
wmask_i	wire logic [Width - 1 : 0]	input
rdata_o	var logic [Width - 1 : 0]	output	Read data. Data is returned one cycle after req_i is high.

×